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AR# 24492

LogiCORE Endpoint Block for PCI Express v1.2 - Why is a PC batch file not generated with the core?

Description

A PC batch or script file for running the core through the Xilinx implementation tools on Windows is not created. What is the syntax for this script?

Solution

Using the syntax below, you can create the two files needed for implementation on a PC.

If you are using a ML505 board, a ready-made script is available at the following ftp link:

http://www.xilinx.com/txpatches/pub/applications/pci/ml505_pci_express_x1_endpoint.zip

The zip file contains a batch file to run the design through the implementation tools. Also, a .prj file is included to properly synthesize the ML505 design. Please consult the README.txt included in the zip file for further instructions. The complete ML505 x1 design for PCI Express is located at: http://www.xilinx.com/products/boards/ml505/pcie.htm

To implement the LogiCORE Endpoint Block for PCI Express v1.2 on Windows, use the following information to create a implement.bat and mem_ep_app_top.prj file. Once created, copy these files into your core directory at the following location:

\pci_express_wrapper\implement

NOTE: The example below assumes the ML555 UCF is being targeted and the BAR Decoder option is enabled. You might need to adjust the syntax below if either of these are not the case.

Contents of implement.bat

REM Clean up the results directory

rmdir /S /Q results

mkdir results

echo 'Synthesizing verilog example design with XST';

xst -ifn mem_ep_app_top.scr

move mem_ep_app_top.ngc .\results\mem_ep_app_top.ngc

cd results

echo 'Running ngdbuild'

ngdbuild -sd "../../example_design" -uc ../../example_design/mem_ep_app_1_ml555_lx50t.ucf -p xc5vlx50t-1-ff1136 mem_ep_app_top

echo 'Running map'

map -p xc5vlx50t-1-ff1136 -logic_opt off -ol std -o mapped.ncd mem_ep_app_top.ngd mapped.pcf

echo 'Running par'

par -ol std -w mapped.ncd routed.ncd mapped.pcf

echo 'Running trce'

trce -u -e 10 -s 1 routed -o routed mapped.pcf

echo 'Running design through bitgen'

bitgen -dw -g plladv_x0y2_use_calc:Yes -g StartupClk:Cclk routed mem_ep_app_top

Contents of mem_ep_app_top.prj

verilog work ../src/pci_express_wrapper.v

verilog work ../src/pcie_gt_wrapper.v

verilog work ../src/bram_common.v

verilog work ../src/pcie_mim_wrapper.v

verilog work ../src/pcie_reset_logic.v

verilog work ../src/pcie_clocking.v

verilog work ../src/pcie_bar_decoder.v

verilog work ../src/pcie_cmm_decoder.v

verilog work ../src/pcie_blk_cf_mgmt.v

verilog work ../src/pcie_top.v

verilog work ../example_design/completer_mem_block_machine.v

verilog work ../example_design/completer_mem_block.v

verilog work ../example_design/completer_mem_block_top.v

verilog work ../example_design/mem_ep_app_top_ml555.v

AR# 24492
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article