The hard_temac_v3_00_b was created to fix a issue in the MDIO interface for Virtex-4 FX production silicon (CES4 or later). However, the new hard_temac_v3_00_b in EDK 8.2i SP2 does not work adequately with pre-CES4 silicon in terms of communicating with the PHY.
This issue pertains to boards with an external PHY that is strapped to an MDIO PHY address of "00000". According to the Ethernet specification (IEEE802), address zero should not be used since it is reserved for broadcast. The broadcast is for writes, so you can write (as an example) a broadcast reset to reset all MDIO devices on the bus with a single write. If you do a broadcast read, you get contention on the bus since every MDIO device will respond, which causes contention on the MDIO bus.
You can work around this issue using one of the following options.
Keep the PCS/PMA PHY in reset for all Ethernet types that are not needed, except for SGMII and 1000BASE-X since these require the use of the internal PCS/PMA TEMAC PHY. All PHYs on the MDIO interface will respond including the internal PHY if it is not held in reset. In the hard_temac, the internal PHY (for 1000BASE-X/SGMII) is not held in reset.
This issue can be resolved by changing the HDL code in v4_1_single_gmii.vhd so that the internal PHY is held in reset and cannot respond to address 0. This file and changes are located at:
phy_config_vector_0_i <= "00000"; -- PCS/PMA logic is not in use
phy_config_vector_0_i <= "10000"; -- PCS/PMA logic is not in use
This issue was also corrected with the following option:
- Pre-CES4 chips (ML403, pre-production ML405/ML410) use hard_temac_v3_00_a.
- CES4 or later chips (production ML405, ML410 boards) use hard_temac_v3_00_b.
If you have a ML403 board that uses CES4 production silicon, you must use hard_temac_v3_00_b.