LogiCORE RapidIO v3.1 Rev 2 Logical Layer - Transmit port locks up

Description

Keywords: v3.1, ip1_i, IP Update 1, serial, parallel, high, speed, high-speed, PHY, logical, design environment, srio, RapidIO

If one Tx port (initiator, target, or maintenance) is sending two large packets, and a second port requests two small packets during transfer of the large packet port's first packet, the large packet port locks up prior to completion of the second packet. Lockup is seen as deassertion on the <port>_rdy_n signal without reassertion.

Solution