We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24497

LogiCORE RapidIO v3.1 Rev 2 Logical Layer - Transmit port locks up


If one Tx port (initiator, target, or maintenance) is sending two large packets, and a second port requests two small packets during transfer of the large packet port's first packet, the large packet port locks up prior to completion of the second packet. Lockup is seen as deassertion on the <port>_rdy_n signal without reassertion.


This issue is fixed in Serial RapidIO v4.1. 

Please upgrade to v4.1 core.

AR# 24497
Date 05/21/2014
Status Archive
Type General Article
Page Bookmarked