Keywords: CORE Generator, ip1_i, IP Update 1, serial, high, speed, high-speed, PHY, design environment, RIO, SRIO, deviceid, RapidIO
Although the core will pass 16-bit device IDs, the Xilinx core is able to store only the lower 8 bits in the Base Device ID CSR, and therefore, might only be enumerated with 16-bit device IDs of 0x0000 - 0x00FF.
16-bit device ID support for the v3.1 (all revisions) core is incomplete. Issues include:
- Inability to access the full 16-bit device ID in the CSR
- Received swrites of > 2 DWs have the lose the last beat through the logical layer
- Message Response lost in receive path