LogiCORE RapidIO v3.1 Rev 2 Physical Layer - Core netlist cannot be loaded into PlanAhead
Description
Keywords: CORE Generator, ip1_i, IP Update 1, serial, high, speed, high-speed, PHY, logical, design environment, RIO, SRIO, floor, planner, layout, NDC2EDIF, comment, RapidIO, illegal, syntax
When converting the RapidIO v3.1 physical layer NGC file to an EDIF format using NGC2EDIF, invalid EDIF syntax is generated. As a result, the core cannot be loaded into PlanAhead. PlanAhead errors out with an invalid format message.
Solution
The problem is caused by the Serial RapidIO netlist, which needs to be corrected in the core source code.This issue will be fixed in Serial RapidIO v4.1 release, expected to be available in February 2007.
If you need a fix for this issue sooner, contact Xilinx Technical Support at:
www.xilinx.com
or at:
http://www.xilinx.com/support/techsup/tappinfo.htm
Please provide three XCO files from v3.1 Core.