We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24501

LogiCORE RapidIO v3.1 Rev 2 Physical Layer - Core netlist cannot be loaded into PlanAhead


When converting the RapidIO v3.1 physical layer NGC file to an EDIF format using NGC2EDIF, invalid EDIF syntax is generated. As a result, the core cannot be loaded into PlanAhead. PlanAhead errors out with an invalid format message.


The problem is caused by the Serial RapidIO netlist, which needs to be corrected in the core source code.  


This issue will be fixed in Serial RapidIO v4.1 release, expected to be available in February 2007. 


If you need a fix for this issue sooner, contact Xilinx Technical Support at: 


or at: 


Please provide three XCO files from v3.1 Core.

AR# 24501
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article