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AR# 24505

MIG 007 - How to map the address for the DDR2 SDRAM user interface to account for auto-precharge bit A10

Description

Keywords: DDR2, DDR, MIG, 007, Precharge, A10, Virtex-II, Virtex-II Pro

For MIG 007 generated DDR/DDR2 SDRAM designs, the address bus, user_input_address read by the controller to generate the memory interface address bus is discontinuous due to the auto-precharge bit A10. The user needs to account for this discontinuity when driving the user backend address by tying low bit A10 and potentially bit A9.

Solution

When a memory device receives a column access, bit 10 (A10) is read to determine if an auto-precharge occurs at the end of the burst. MIG designs do not support auto-precharge but reserve bit A10 for users wanting to implement custom auto-precharge logic. If this custom logic is not implemented, A10 needs to be set to 0 to disable auto-precharge.

MIG 007 does not force bit A10 to zero and so the user MUST tie bit 10 of the user backend address to zero. If A10 was set to one, the memory device would expect an auto-precharge that the MIG controller does not send.

Based on the number of column bits, the user needs to drive the user backend address bus, user_input_address, differently to account for the auto-precharge bit A10. When interfacing to DDR/DDR2 devices with 10 or more columns bits, user_input_address [10] is ignored by the controller logic. When interfacing to DDR/DDR2 devices with only 9 column bits , user_input_address[10:9] are ignored. The user needs to be aware of these unused bit(s) and drive the user backend address bus, user_input_address appropriately.

An example of ignoring only user_input_address[10] is for a DDR2 bus interfacing to a single Micron MT47V32M16 (512Mbit, x16 wide) device. Here, the address bus accesses 2^25 word locations (10 column + 13 row + 2 bank = 25 bits). The user backend address should be driven as shown below, tyling bit user_input_address[10] low:
user_input_address[9:0] = COLUMN_ADDR[9:0]
user_input_address[10] = 0 / *unused, tie off */
user_input_address[23:11] = ROW_ADDR[12:0]
user_input_address[25:24] = BANK_ADDR[1:0]

An example of ignoring user_input_address[10:9] is for a DDR2 bus interfacing to a single Micron MT47V16M16 (256Mbit, x16 wide) device. Here, the address bus accesses 2^24 word locations (9 column + 13 row + 2 bank = 24 bits). The user backend address should be driven as shown below, skipping bits user_input_address[10:9]:
user_input_address[8:0] = COLUMN_ADDR[8:0]
user_input_address[10:9] = 0 / *unused, tie two bits off */
user_input_address[23:11] = ROW_ADDR[12:0]

NOTE: If the column address is greater than 10, the MSBs greater than 10 would start at user_input_address[11] and user_input_address[10] would be tied to zero.
AR# 24505
Date Created 09/04/2007
Last Updated 04/06/2009
Status Archive
Type General Article