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AR# 24518

14.x/2012.x Timing/Constraints - How can the SYSTEM_JITTER constraint be used?

Description

How can a value for the SYSTEM_JITTER constraint be generated?

Solution

The SYSTEM_JITTER constraint is used to represent the power noise, board noise, and any extra jitter of the overall system.

To include the clock edge noise and power noise into the constraint value, two measurements should be performed:

  • the clock edge (T2 - T1)/(Virtex_FPGA-V1) where, for example:
    • T1 and V1 are time and voltage measured at 20% of the signal edge
    • T2 and Virtex_FPGA are time and voltage measured at 80% of the signal edge
  • the power noise Vn

With these, the SYSTEM_JITTER should then be Vn*(T2 - T1)/(Virtex_FPGA-V1)

A suggested SYSTEM_JITTER value is 300 ps. The default SYSTEM_JITTER value for many device families are between 50-70 ps.

AR# 24518
Date Created 09/04/2007
Last Updated 01/24/2013
Status Active
Type General Article
Tools
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