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AR# 24541

MIG v1.7 - Release Notes and Known Issues for ISE 9.1i MIG v1.7

Description

This Answer Record contains the Release Notes for MIG v1.7, and includes the following:

  • Software Support
  • Platform Support
  • Device Support
  • New Features
  • Bug Fixes
  • Known Issues
  • Installation Instructions
  • Getting Started

Solution

Software Support

  • All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i.

Platform Support

  • Microsoft Windows XP (32 bit)

Device Support

  • All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported.

New Features

General New Features and Changes

  • Supports "Create New Memory Part" for all the designs.
  • DDR and DDR2 SDRAM designs for Spartan-3A.
  • DDR SDRAM is supported for Virtex-5.
  • VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM.
  • MIG now pops up the design notes specific to the generated design.
  • Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs.
  • ECC check box changed to Combo box to support Pipelined and Un-pipelined modes.
  • Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2.
  • Pops up an information note if user selects an invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A.
  • Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST".
  • Default setting "DCI for Address and Control " is changed to "unChecked".
  • Frequency slider is changed to editable box in the GUI.
  • Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names.
  • Removed console window when running MIG through CORE Generator.
  • WASSO table (Set Advanced Options) accepts only numeric characters.
  • The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32.
  • Provided web links for all XAPPs in the docs folder of the designs.
  • Provided link to Data Sheet instead of Log Sheet in the output window.
  • Support of Constraint "CONFIG PROHIBIT" while reading the .ucf in the reserve pins window.
  • WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank.
  • The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition.

Virtex-5 New Features and Changes

DDR2 SDRAM

  • New controller with several high-performance features. All the features are described in detail in the Application Notes.
  • Enhanced data calibration algorithms for higher reliability.
  • Bank Management feature is supported.
  • Supports VHDL.
  • The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear.
  • The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus.
  • Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to all the memory interface signals.

c. Signals such as "Error" outputs are not part of the WASSO count.

DDR SDRAM

  • This is a new design for MIG. Supports Verilog and VHDL.
  • Bank Management feature is supported.
  • The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus.

The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear.

QDRII SRAM

  • Added support for VHDL.
  • Added support for 72-bit designs.
  • Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay.
  • Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6
  • A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was made for timing reasons.
  • Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to the output signals only.

Virtex-4 New Features and Changes

DDR2 SDRAM Direct Clocking

  • Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design.
  • Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins.
  • There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
  • ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options.
  • DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers.
  • Removed all TIGs in UCF. The reset signal is now registered in every module.
  • The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
  • SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
  • Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
  • Replaced `defines with localparams for Verilog.
  • Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
  • Several state machines now use "One-Hot Encoding".
  • Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
  • Signal INIT_DONE is brought to top module.
  • Removed the UniSim primitive components declaration from VHDL modules.
  • We now support all multiples of 8-bit data widths even for x16 memory devices.
  • We support memory devices of speed grades -3 and -667.
  • Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to all the memory interface signals.

c. Signals such as "Error" outputs are not part of the WASSO count.

DDR2 SDRAM SERDES Clocking

  • Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note.
  • There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
  • Support for ODT.
  • DQS# Enable is selectable from GUI through Mode registers.
  • Removed all TIGs in UCF. The reset signal is now registered in every module.
  • The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
  • SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
  • Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
  • Replaced `defines with localparams for Verilog.
  • Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
  • Removed the UniSim primitive components declaration from VHDL modules.
  • We now support all multiples of 8-bit data widths even for x16 memory devices.
  • Signal INIT_COMPLETE is brought to top module.
  • Memory devices of speed grades -5E and -40E are now supported.
  • Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to all the memory interface signals.

c. Signals such as "Error" outputs are not part of the WASSO count.

DDR SDRAM

  • There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
  • Removed all TIGs in UCF. The reset signal is now registered in every module.
  • The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
  • SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
  • Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
  • Replaced `defines with localparams for Verilog.
  • Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
  • Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
  • Removed the UniSim primitive components declaration from VHDL modules.
  • We now support all multiples of 8-bit data widths even for x16 memory devices.
  • The signal "init_done" is now a port in the top module.
  • Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to all the memory interface signals.

c. Signals such as "Error" outputs are not part of the WASSO count.

RLDRAM II

  • There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
  • Removed all TIGs in UCF. The reset signal is now registered in every module.
  • The design now uses CLK0, instead of CLK50 and div16clk.
  • CLK200 is changed to differential clocks in mem_interface_top module (Design top).
  • The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal.
  • Removed unused parameters from the parameter file.
  • Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
  • Replaced `defines with localparams for Verilog.
  • Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
  • Removed the UNISIM primitive components declaration from VHDL modules.
  • The signal "INIT_DONE" is now a port in the top module.
  • Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8.
  • Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets.
  • The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file.
  • Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO count is applied on output signals only for SIO memory types.

c. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool.

QDRII SRAM

  • There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
  • Timing for the signal USER_QEN_n has been changed it is one cycle late. A register for this signal has moved from the controller to the user logic.
  • Supports generation of designs with out DCM.
  • Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC.
  • Removed all TIGs in UCF. The reset signal is now registered in every module.
  • The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
  • Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
  • Replaced `defines with localparams for Verilog.
  • Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
  • Removed the UNISIM primitive components declaration from VHDL modules.
  • The signal "DLY_CAL_DONE" is now a port in the top module.
  • The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
  • Added support for DDR Byte writes.
  • Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to the output signals only.

c. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool.

DDRII SRAM

  • There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
  • Timing for the signal USER_QEN_n has been changed -it is one cycle late. A register for this signal has moved from the controller to the user logic.
  • Supports generation of designs with out DCM.
  • Part CY7C1526V18-250BZC has been removed from Memory Parts list.
  • Removed all TIGs in UCF. The reset signal is now registered in every module.
  • The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
  • Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
  • Replaced `defines with localparams for Verilog.
  • Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
  • Removed the UNISIM primitive components declaration from VHDL modules.
  • The signal "DLY_CAL_DONE" is now a port in the top module.
  • The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
  • Added support for DDR Byte writes.
  • Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.

a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.

b. WASSO is applied to all the memory interface signals.

c. Signals such as "Error" outputs are included in WASSO count.

Spartan-3, Spartan-3E, Spartan-3A New Features and Changes

  • There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
  • Removed all TIGs in UCF. The reset signal is now registered in every module.
  • Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
  • Replaced `defines with localparams for Verilog.
  • Removed the UNISIM primitive components declaration from VHDL modules.
  • We now support all multiples of 8-bit data widths even for x16 and x4 memory devices.
  • The signal "cntrl0_data_valid_out" is now a port in the top module.
  • DQS# Enable, burst type and ODT can be selected from the MIG GUI through the Mode registers.
  • Board files for Spartan-3E starter kit provided in VHDL and Verilog.
  • Implemented several changes to the controller to improve timing.
  • Changed the Spartan-3/3E pin allocation rule for increased efficiency. The previous rule was that DQs corresponding to a particular DQS could be within 5 tiles above and 5 tiles below the DQS. Now, the DQs can be 5 tiles above and 6 tiles below the DQS.
  • Support for Spartan-3A.

Bug Fixes

  • Corrected the pin allocation for Virtex-4/-5 devices when "DCI for data/DCI for Address" is selected.
  • Removed the support of Serdes Clocking type for the FPGAs which do not have PMCDs.
  • Modified the default bank selections for all the designs.
  • Removed the PAD numbers column in Edit signal names.
  • Part xc4vfx140-ff1760 has been removed from V4-FPGA list, as this part is not supported by ISE.
  • Displays only supported data widths by Spartan devices.
  • Removed unwanted parameters that are coming up in 'View Memory Details' for all designs of Virtex-5, Virtex-4 and Spartan-3/-3E/-3A.
  • Made some minor enhancements to Verify My UCF. Verifies if the DQS is allocated to 'P' pin of CC pair and corrected some of the messages.
  • (Xilinx Answer 24448) regarding information on problems exiting initial startup calibration for certain configurations of Virtex-4 DDR2 SDRAM controllers.
  • -Because of a bug in IP Update 1 FIFO Generator v3.1, VHDL simulations of RLDRAMII caused the following failure:

FAILURE: Use of behavioral models for Virtex-4 and Virtex-5 built-in FIFO configurations is not currently supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information. "SEVERITY FAILURE"

(Xilinx Answer 23831) contains more information in obtaining 8.2i IP Update 2.

Known Issues

  • Please see (Xilinx Answer 24979) for general CORE Generator support items.
  • Please see (Xilinx Answer 24965) for information regarding the incorrect setting for jumper location 'P10' specified in the ChipScope (.cpj) and Readme.txt files output with the ML461 board files when using the DDR2 SDRAM Direct Clocking design.
  • Please see (Xilinx Answer 24432) for information on mapping the user interface address to account for the auto-precharge bit A10 for Virtex-4 DDR/DDR2 SDRAM controllers and general information on mapping the user interface address for Virtex-5 DDR/DDR2 SDRAM controllers.
  • Please see (Xilinx Answer 24993) for more information regarding stage 4 calibration of the Virtex-5 DDR SDRAM design not finding optimal calibration point or not completing.
  • Spartan-3/-3E/-3A x4 designs are only supported for data widths up to 72-bits. Wider interfaces implement with incorrect local clock routes when top/bottom banks are selected. This issue is observed only for x4 memory component and for top/bottom banks. This will be fixed in MIG 1.8.
  • MIG generates an 8-bit data interface for Spartan-3/-3E/-3A designs when top/bottom banks are selected even if the FPGA has more available pins to allocate larger data widths. The GUI allows the user to select different data widths but the design generated is always 8-bits. This only occurs when the top/bottom banks are selected. To work around this, the user should select either left or right banks, select the required data width, and then change the bank selection to top/bottom. This will be fixed in MIG 1.8.
  • In Spartan-3/-3E/-3A designs, users can select "Write Pipe Stages" from "Set Advanced Options." The default value of "Write Pipe Stages" is 4. If any other value (3,2,1,0) is selected, the test_bench module should include the extra pipe stages on the write data and data mask signals. This is missing in the design. There is no issue for the default Write Pipe Stage of 4. This will be fixed in MIG 1.8.
  • Please see (Xilinx Answer 24964) for information on the "Verify My UCF" option in the MIG GUI.
  • You should be aware of the stepping level of your target Spartan-3 devices and how this affects the maximum frequency achievable for the memory component that is generated. The MIG tool does not adjust the frequency for any particular stepping level in use. Please consult the relevant device data sheets or errata for more information on stepping. These documents are located at:

http://www.xilinx.com/support/library.htm.

  • MIG only supports Synplicity and XST. When setting the "Vendor" (CoreGen Project Options > Generation tab, Flow Settings, Vendor), only Foundation ISE or Synplicity should be selected. If a vendor outside of Synplicity or Foundation ISE is selected, MIG will generate ISE (XST) files. However, this does not work when "Mentor HDL" is selected. DO NOT use "Mentor HDL". It is not supported.

MIG v1.7 Installation Instructions

The MIG tool is accessible via the Xilinx CORE Generator System, starting with MIG

version 1.3. There are two ways to install MIG.

Method 1 Download Center

1. Users must verify that they have ISE 9.1i Service Pack 1 and the latest IP Update from the Download Center at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp.

2. The MIG zip file is available for download from the Download Center when the following options are selected:

  • Select a Download Type ISE IP Update
  • Select an ISE Version 9.1i
  • Select an Operating System Windows

3. Download the zip file and save it to a temporary directory.

4. Extract the .zip file archive to a temporary directory.

5. Run the setup.exe executable to install MIG 1.7. Select the location of your ISE 9.1i installation as the destination directory. The Xilinx design tools installation directory is typically located at "C:\Xilinx," if the installation defaults were used. You can verify the location of the Xilinx install by entering the following on the DOS command line:

echo %XILINX%

Method 2 WebUpdate

1. The CORE Generator system is launched by selecting Start -> Xilinx ISE 9.1i -> Accessories -> CORE Generator from the Windows Start menu.

2. When the CORE Generator GUI opens, select Tools -> Software Updates.

3. The CORE Generator system displays a dialog box with a warning indicating that it will exit after the installation is complete. Click the OK button.

4. The CORE Generator system connects to www.xilinx.com. Users who are behind a firewall might have to enter their appropriate proxy settings.

5. The Xilinx WebUpdate dialog box opens and displays a panel listing the available updates.

6. Select ISE9.1i MIG1.7 and click the Install Selected button. The program might indicate that other installs are required. These informational messages can be accepted. The CORE Generator system downloads and installs the requested products and exits.

NOTE: The installation process must not be interrupted. During this process, various pop-up messages must be accepted. If other windows are open, the pop-ups might be hidden behind them.

Getting Started

These steps launch the MIG tool:

1. The CORE Generator system is launched by selecting Start -> Xilinx ISE9.1i -> Accessories -> CORE Generator.

2. Create a CORE Generator project.

3. The Xilinx part must be correctly set because it cannot be changed inside the MIG tool. Virtex-4 and Spartan-3/Spartan-3E devices are supported. Select the part via the part's Project Options menu in the CORE Generator system. The Generation tab is used to select between Verilog or VHDL by "design entry" under "flow". The "flow settings" and "vendor" must be chosen appropriately. The choices are "Synplicity" for Synplify, "ISE" for XST, and "Mentor Graphics (HDL)" for Precision. Precision is only supported for the Spartan family.

4. Remember the location of the CORE Generator project directory. The "View by Function" tab to the left shows the available cores organized into folders.

5. The MIG tool is launched by selecting Memories & Storage Elements -> Memory Interface Generator -> MiG.

6. The name of the module to be generated is entered in the Module Name text box. After entering all the parameters in the GUI, click Generate to generate the module files in a directory with the same name as the module name in the CORE Generator project directory.

7. After generation, the GUI is closed by selecting the Dismiss button. The "Generated IP" tab to the left lists the generated modules. The generated ise_flow.bat script or the ISE GUI is used to manually add the generated HDL files to a project.

Additional Information

You can access additional MIG and memory-related information at:

http://www.xilinx.com/products/design_resources/mem_corner/index.htm

NOTE: To access this URL, you must register specifically for the Memory Interface Generator product.

If you have comments, questions, or problems, contact Xilinx Technical Support at:

http://www.xilinx.com/support/techsup/tappinfo.htm

AR# 24541
Date Created 09/04/2007
Last Updated 06/09/2015
Status Active
Type General Article
Tools
  • ISE - 9.1i
IP
  • MIG