In my design, the BUFR output signal is running at 350 MHz, but PAR and timing issue a warning that the current 350 MHz clock is over the Minimum Period of 250 MHz. When is this going to be fixed?
The maximum BUFR input frequency is 710 MHz, but the maximum output frequency is 250 MHz for a -11 speed grade.
This problem has been fixed in the latest 9.1i Service Pack available at:
The first service pack containing the fix is 9.1i Service Pack 1.