UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24552

LogiCORE FIFO Generator v3.3 - Release Notes and Known Issues for 9.1i IP Update1 (9.1i_IP1) and 9.1i IP Update2 (9.1i_IP2)

Description

Keywords: CORE, CORE Generator, COREGen, IP, update, 8.2i, ip2_im, FIFO, generator, fifogen, asynchronous, synchronous, common, clocks, memory, block RAM, BRAM, RAMB16, FIFO16, asynch, asymmetric, non-symmetric, first, word, fall, through, fwft

This Release Note and Known Issues is for the FIFO Generator v3.3 Core released in 9.1i IP Update 1 and contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues
- Device Issues

For installation instruction for IP Update #1, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24307)
For installation instruction for IP Update #2 and design tools requirements, see (Xilinx Answer 24628).
Installing IP Update # 2 upgrades the core to "Rev 1" status and enables Spartan3A DSP support.
All known issues mentioned in this Answer Record is still applicable.


Solution

New Features in v3.3
ECC support for Virtex-5 built-in FIFO configuration

Bug Fixes in v3.3
CR 423076: If the reset pin is not selected, the Reset Type text on page 6 of the GUI Summary is displayed incorrectly as "Asynchronous" instead of "Not Selected"
CR 422495: Core cannot be generated for Independent Clock Block RAM FIFOs with input_depth=16 and output_depth=128, or input_depth=128 and output_depth=16

General Information
(Xilinx Answer 22014) When using FIFO Generator Core, the allowed data count width is less than it should be
(Xilinx Answer 22722) FIFO Generator Core now includes User Guide in addition to data sheet. Where can I find the User Guide for the FIFO Generator?
(Xilinx Answer 24712) How to test user logic that triggers ECC SBITERR and DBITERR outputs in FIFO Generator.

Known Issues in v3.2
(Xilinx Answer 24802)"Estimated FIFO usage" feature in the last page of the GUI is not accurate when ECC feature is enabled
(Xilinx Answer 24003) NCELab issues warnings: "memory index out of declared bounds" in simprims_ver_virtex5_source.v or unisim_ver_virtex5_source.v during Verilog structural and timing simulations in NCSIM for Virtex-5 block RAM FIFOs. The simulation will be successful, and the warnings can be ignored
(Xilinx Answer 23691) Behavioral models are not supported for the built-in FIFO
(Xilinx Answer 20278) PROG_EMPTY and PROG_FULL can produce false-assertions
(Xilinx Answer 20291) Simulation Warning: "*/X_FF RECOVERY Low VIOLATION ON SET WITH RESPECT TO CLK"
(Xilinx Answer 20271) Simulation error on RESET: "Error: /proj/xbuilds/G.36/verilog/src/simprims/X_RAMB16.v(4289): $hold(..."

Device Issues
Please be aware of Virtex-4 and Virtex-5 Errata posted on
http://www.xilinx.com/support/mysupport.htm
FIFO Generator Core with block Ram configuration is subject to all block RAM issues listed in the errata.

Documentation Changes
FIFO Generator v3.3 User Guide: Clarified the behavior of Read Data Count (RD_DATA_COUNT) and Write Data Count (WR_DATA_COUNT)

FIFO Generator v3.2 Known Issues
-The FIFO Generator v3.2 is now obsolete. Please upgrade to the latest version of the core.
For information on existing FIFO Generator v3.2 issues, see (Xilinx Answer 23847).

FIFO Generator v3.1 Known Issues
-The FIFO Generator v3.1 is now obsolete. Please upgrade to the latest version of the core.
For information on existing FIFO Generator v3.1 issues, see (Xilinx Answer 23490).

FIFO Generator v2.3 Known Issues
-The FIFO Generator v2.3 is now obsolete. Please upgrade to the latest version of the core.
For information on existing FIFO Generator v3.1 issues, see (Xilinx Answer 22302).
AR# 24552
Date Created 09/04/2007
Last Updated 04/02/2007
Status Active
Type General Article