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AR# 24553

LogiCORE Distributed Memory Generator v3.3 - Release Notes and Known Issues for 9.1i IP Update 1 (9.1i_IP1) and 9.1i IP Update 2 (9.1i_IP2)

Description


This Release Note is for the Distributed Memory Generator Core v3.3 released in the 9.1i IP Update 1, and contains the following information: 
- General Information 
- New Features 
- Bug Fixes 
- Known Issues 
 
For installation instructions for IP Update #1 and design tools requirements, see (Xilinx Answer 24307)
For installation instructions for IP Update #2 and design tools requirements, see (Xilinx Answer 24628)
Installing IP Update # 2 upgrades the core to "Rev 1" status and enables Spartan3A DSP support. 
All known issues mentioned in this Answer Record is still applicable.

Solution


General Information 
 
The Xilinx Distributed Memory Generator v3.3 LogiCORE should be used in all new designs for supported families wherever a distributed memory is required. This core supersedes all versions of the previously released Distributed Memory LogiCORE.  
 
New Features 
 
No new features in this release. 
 
Bugs Fixed in v3.3 
 
CR 415385 - Dist_Mem_Gen failed when Width = 1 and Family = Virtex4.  
CR 326740 - Excessive register duplication in distributed memory synthesis.  
(Xilinx Answer 24617) - Simulation warning "MIF file size does not match memory size" when MIF file is used. 
 
Known Issues in v3.3  
 
(Xilinx Answer 21393) - When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate.
AR# 24553
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article