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AR# 24555

LogiCORE Block Memory Generator v2.4 - Release Notes and Known Issues for 9.1i IP Update 1 (9.1i_IP1) and IP Update 2 (9.1i_IP2)

Description

This Release Note is for the Block Memory Generator Core v2.4 released in 9.1i IP Update 1 and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions for IP Update #1 and design tools requirements, see (Xilinx Answer 24307).

For installation instructions for IP Update #2 and design tools requirements, see (Xilinx Answer 24628).

Installing IP Update # 2 upgrades the core to "Rev 1" status and enables Spartan3A DSP support.

All known issues mentioned in this Answer Record is still applicable.

Solution

General Information

The Xilinx Block Memory Generator v2.4 LogiCORE should be used in all new Virtex-5, Virtex-4 /-4 XA, Virtex-II, Virtex-II Pro, Spartan-II/E and Spartan-3 /-3E /-3E XA /-3A /-3 XA designs wherever a block memory is required. This core supersedes the Single Port Block Memory v6.2 and Dual Port Block Memory v6.3 cores, but is not a direct drop-in replacement. A Block Memory Migration Kit is available on Xilinx.com to convert Single Port Block Memory v6.2 and Dual Port Block Memory v6.3 cores to the newer Block Memory Generator Core format.

See the Block Memory Core Migration Kit available at:

http://www.xilinx.com/ipcenter/blk_mem_gen/blk_mem_gen_migration_kit.htm
Also see (Xilinx Answer 24848) for known issues of the migration kit.

(Xilinx Answer 24712) How to test user logic that triggers ECC SBITERR and DBITERR outputs in Block Memory Generator.

New Features in v2.4

- Support for ECC (built-in Hamming error correction) in Virtex-5

Bug Fixes in v2.4

CR 429967: Block Memory Generator wastes resources (is non-optimal for certain configurations)

CR 415531: Block Memory Generator GUI displays unselectable options

Known Issues in v2.4

(Xilinx Answer 23688) Block Memory Generator GUI will not open on Linux and Solaris when project directory is in "$XILINX"

(Xilinx Answer 23744) Invalid address input can cause the core to generate Xs on the DOUT bus

(Xilinx Answer 24034) Block Memory Generator Core takes a long time to generate

(Xilinx Answer 24313) The core might issue unexpected outputs and simulation warning: "# ** Warning: Functional warning at simulation time ..."

(Xilinx Answer 24804) ERROR:sim:166 - An internal error has occurred. Closing core customization GUI.

(Xilinx Answer 24860) When using Single Port ROM/RAM, BitGen gives "ERROR:PhysDesignRules:1530 - Dangling pins on block:../blk_mem_generator/SP.CASCADED_PRIM36.."

Device Issues

The Virtex-4 and Virtex-5 Errata is located at:

http://www.xilinx.com/support/mysupport.htm
The Block Memory Generator Core is subject to all block RAM issues listed in the Errata.

Block Memory Generator v2.3 Known Issues

-The Block Memory Generator v2.3 is now obsolete. Please upgrade to the latest version of the core.

For information on existing Block Memory Generator v2.3 issues, see (Xilinx Answer 24229).

Block Memory Generator v2.2 Known Issues

-The Block Memory Generator v2.2 is now obsolete. Please upgrade to the latest version of the core.

For information on existing Block Memory Generator v2.2 issues, see (Xilinx Answer 23849).

AR# 24555
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article