We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24582

Virtex-5 Configuration Errata - Reconfiguration results in incorrect configuration


When reconfiguring with a different bitstream on an already configured Virtex-5 LX/LXT/SXT engineering sample (ES) device, in rare cases a static LUT input can be inverted.


When the following sequence occurs, there is a small possibility that a LUT in a Virtex-5 ES design will not properly initialize.

1. A Virtex-5 ES design containing an unregistered combinatorial feedback loop has been programmed into the FPGA.

2. This combinatorial feedback loop is disconnected in a new or modified design and is subsequently loaded into the FPGA.

In this case, reconfiguration of the device requires power cycling. This errata applies only to Virtex-5 LX/LXT/SXT Platform engineering samples.

Information on specific Virtex-5 devices affected by this errata is available on the Xilinx Web site at:


AR# 24582
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article