We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24584

LogiCORE Fibre Channel v3.1 - Release Notes and Known Issues for 9.1i IP Update 1 (9.1i_IP1)


This Answer Record contains the Release Notes for the LogiCORE Fibre Channel v3.1 Core that was released in the 9.1i IP Update #1, and includes the following: 


- New Features 

- Bug Fixes  

- Known Issues  


For installation instructions and design tools requirements, see (Xilinx Answer 24307).


New Features  


- Support for the ISE 9.1i design tools release has been added. 

- Support has been added for Virtex-5 LXT and SXT family devices. 


Bug Fixes  


- All fixes to v2.1 rev1 have been rolled into this version of the core. (Xilinx Answer 22323) 

- CR 433994, When using applybackpressure, more than one RRDY can be sent at a time if the transmit and receive frames align just right internally to the core. 


Known Issues in v2.1 


-For Virtex-II Pro board designs to avoid BER failures, it is important to insure that board meets Virtex-II Pro MGT specifications. For more information, see (Xilinx Answer 25035).

AR# 24584
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article