This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v4.4 that was released in 9.1i IP Update #1, and includes the following:
- New Features in v4.4
- Bug Fixes in v4.4
- Known Issues in v4.4
For installation instructions and design tools requirements, see (Xilinx Answer 24307).
New Features in v4.4
- This release of the Virtex-4 Embedded MAC Wrapper is an update to be compatible with ISE 9.1i. It is fully tested on the new design tools version.
- Several architectural changes have been made. The IDELAY component is used in GMII and RGMII PHY standards to meet setup and hold timing. This delay element was moved from the clock to the data path, in order to make meeting timing easier. A constraint for setup and hold timing has been added to ensure compliance with the appropriate specifications. Please see the Getting Started Guide for more information on these new constraints.
- The GMII and RGMII data, control and clock pins have now been LOCed down to illustrate how these pins should be grouped together according to the recommended design practices. New constraints have also been added on several paths that were previously unconstrained.
- The IDELAYCTRL block reset pulse has been extended to 50 ns to conform with the latest recommendations.
- Updated Virtex-4 RocketIO attributes to conform to latest recommendations
Bug Fixes in v4.4
-CR423845 - When using Dual 1000BASE-X or SGMII if one MGT is not in use both with EMACs in tile will be put in reset.
-CR428354 - GUI Check boxes for In-band FCS Enable, VLAN Enable and Half-Duplex Enable are sometimes ignored/removed when generating core
-CR432457 - In example functional simulation some of signals added to waveform are incorrect and undefined
Known Issues in v4.4