This Answer Record contains the Release Notes for the LogiCORE XAUI v7.1 Core, which was released in 9.1i IP Update 1, and includes the following:
- New Features
- Bug Fixes
- Known Issues
For installation instructions and design tools requirements, see (Xilinx Answer 24307).
- Support added for ISE 9.1i
- Support added for Virtex-5 SXT
- Removed requirement to reset RocketIO Transceivers after a powerdown
- Updated Virtex-4 RocketIO Wrappers with changes from RocketIO Wizard 1.4
- Updated Virtex-5 RocketIO Wrappers with changes from RocketIO GTP Wizard 1.4
- Virtex-5 RocketIO Phase-Alignment Circuit incorrect (CR 433243)
The previous Virtex-5 RocketIO Phase-Alignment circuit would set TXENPHASEALIGN Low after phase alignment was completed. This now remains High.
- Virtex-5 RocketIO Phase-Alignment Circuit should be held in reset until there is a stable clock and the GTP PLL has locked. (CR 433696)
The previous Virtex-5 block-level module would hold the phase alignment circuit in reset only until there was a stable clock. This led to the possibility of doing phase alignment before the GTP PLL had obtained lock, and data errors were a result. The phase alignment circuit is now held in reset until there is a stable clock and the GTP PLL has locked.
- The following bug fixes delivered in the v7.0 rev1 patch for this core have been rolled into v7.1:
- NCsim fails to elaborate rocketio_wrapper.vhd (CR 427037)
- Updated PMA_COM_CFG setting for Virtex-5 TX Buffer Bypass Mode (CR 429007)
The PMA_COM_CFG setting is now set in the UCF for correct operation in this mode.
- CB_SEARCH counter setting of enable_cnt_r instead of enable_cnt2_r in chanbond_monitor.vhd causes counter to be optimized away (CR 429052).
- Width of mgt_rx_reset in Verilog Virtex-5 block level is incorrect (CR 430496)
1. Virtex-4 Timing simulation fails with error "Transmit fail: data mismatch at XAUI serial interface." For more information, see (Xilinx Answer 24678).
2. Virtex-5 Timing simulation fails with error "Testbench timed out." For more information, see (Xilinx Answer 24677).
3. Virtex-5 Timing simulation fails with error "Transmit fail: data mismatch at XAUI serial interface." For more information, see (Xilinx Answer 24729).
4. Virtex-5 LXT ES silicon requires transmit signals between the fabric and GTP to be registered and locked down in order to meet timing. These were included in v7.0 of the XAUI core but have not been included in v7.1 as they are not needed for production devices. If Virtex-5 ES silicon must be targeted, the wrapper file for the GTP can be regenerated with the RocketIO wizard. Refer to (Xilinx Answer 24168) for instructions on how to generate the file.
5. Virtex-4 VHDL example design has an undriven signal that causes Synplify to trim GT11 init blocks. Refer to (Xilinx Answer 25024) for more information.
6. Virtex-5 Verilog example design has an unconnected signal that causes tx phase alignment to not function correctly in hardware. Refer to (Xilinx Answer 25381) for more information.
7. After further Characterization, the Virtex-5 RocketIO GTP Transceiver Users Guide v1.3 and RocketIO GTP Wizard v1.5 have updated attributes and the transmit phase alignment procedure for XAUI. Refer to (Xilinx Answer 25386) for more information on how to get these updates.
8. Virtex-4 Verilog example design has GT11 comma alignment inputs driven by incorrect signals. This could cause rx comma alignment/synchronization to not function correctly in hardware. Refer to (Xilinx Answer 29058) for more information.
9. The GT11_INIT State Machine that is included in the Virtex-4 RocketIO Wizard example design contains an asynchronous input that can cause the state machine to go into an unknown state. Refer to (Xilinx Answer 25469) for more information.
10. For the XAUI GT11 configuration, the recommended RocketIO wizard setting has changed for RXRCPADJ from "110" to "011". Refer to (Xilinx Answer 24656) for more information.