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AR# 24591

LogiCORE Tri-Mode Ethernet MAC v3.3 and v3.3.1 - Release Notes and Known Issues for 9.1i IP Update 1 (9.1i_IP1) and IP Update 2 (9.1i_IP2)


This Answer Record contains the Release Notes for the LogiCORE Tri-Mode Ethernet MAC v3.3 Core (released in the 9.1i IP Update 1), and LogiCORE Tri-Mode Ethernet MAC v3.3.1 Core (released in 9.1i IP Update 2). It includes the following:

- New Features in v3.3

- New Features in v3.3.1

- Bug Fixes in v3.3

- Known Issues in v3.3

For installation instructions and design tools requirements, see (Xilinx Answer 24307). The v3.3.1 Core adds support for Spartan-3A DSP. For v3.3.1 installation instructions and design tools requirements, see (Xilinx Answer 24628).


New Features in v3.3

- Support added for ISE 9.1i.

- Moved IDELAY/IODELAY components in Virtex-4/Virtex-5 implementations off the relevant clock input and onto data and control signals.

- Example design FIFOs updated to provide a more robust solution.

New Features in v3.3.1

- Support added for Spartan-3A DSP.

Bug Fixes in v3.3

- CR 430693: IDELAYCTRL reset pulse needs to be extended to meet new guidelines for Virtex-4 and Virtex-5 devices.

- CR 428521: Modified address filter to correctly count statistics for runt frames (<= 5 bytes).

- CR 432150: Updated address filter to correctly recognize Multicast Pause frames (Xilinx Answer 24554).

Known Issues in v3.3

- The example design ucf is missing a period constraint on the rx clock. For more information, see (Xilinx Answer 29935).

- The LogiCORE Tri-Mode Ethernet MAC v3.3 data sheet DS297 lists Spartan-3, Spartan-3E, Spartan-3A devices as requiring (-5) speed grade. This is incorrect. Timing can be met using the slower (-4) speed grade. This will be updated in the next release of the data sheet.

- In the example design UCF, the reset input is not assigned an IOSTANDARD. This means that the reset pin is being set to the device default instead of the same IOSTANDARD as other pins in the example design. For Spartan-3E, this means that the reset will be set to LVCMOS, while every other pin is LVTTL and can cause a failure of:


For more information on this failure, see (Xilinx Answer 24716).

This failure can be avoided by adding the following line to the UCF:


AR# 24591
Date 12/15/2012
Status Active
Type General Article
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