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AR# 24593

Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper v1.2 - Release Notes and Known Issues for 9.1i IP Update 1 (9.1i_IP1)


This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v1.2, which was released in the 9.1i IP Update 1 and includes the following:

-General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 24307).


General Information

- Supports automatic generation of HDL wrapper files for the Virtex-5 LXT Tri-Mode Ethernet MAC

- Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII and 1000Base-X PCS/PMA configurations are supported)

- Provides a FIFO-based example design

- Provides a demonstration testbench for the selected configuration

New Features

- ISE 9.1i support

- Moved the clock buffers out of the EMAC IP block level into the example design wrapper to improve clock resource sharing across multiple cores

- Separate UCF files are now provided for the block, the LocalLink and the example design levels of the wrappers. This helps users to select the correct constraints for the design

- RGMII Configurations: Moved the IDELAY components from the clock input to the data inputs providing a more robust RGMII solution

Bug Fixes

- None

Known Issues

- TEMAC DCRBASEADDR inconsistent between VHDL and Verilog.

VHDL DCR bus simulations fail in ModelSim PE; this is a problem with ModelSim PE only. ModelSim SE and IUS simulations work correctly. The bug results in the bits of the EMAC#_DCRBASEADDR generic in the VHDL UniSim and SimPrim models being flipped. Both functional and timing simulations are affected.

To work around this issue, set EMAC#_DCRBASEADDR to a symmetric value, e.g., 0x81 or 0xC3.

- For designs using 1000BASE-X or SGMII, the Virtex-5 LXT and SXT ES devices require transmit signals between the fabric and GTP to be registered and locked down to meet timing. These registers are not needed for production devices and are not included in version 1.2 of the core. The previous version of the core, v1.1, did have these registers. Refer to (Xilinx Answer 24165) for more information.

- Virtex-5 Timing simulation might fail with transmit data mismatch. For more information, see (Xilinx Answer 24729).

- To use the Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper v1.2 files in the Project Navigator GUI or a script that runs only through synthesis once, the following changes must be made to the HDL and UCF. For more information, see (Xilinx Answer 25219).

- Virtex-5 GTP Users Guide and wizard updated the default recommended termination settings after this version of the core was released. This changed External AC coupling only and the attribute RCV_TERM_VTTRX was changed from True to False. See the GTP Users Guide RX Termination section for more information. This attribute update has been made in the v1.3 and later cores.

AR# 24593
Date 12/15/2012
Status Active
Type General Article
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