This Release Notes and Known Issues Answer Record is for the Virtex-4/-II Pro Aurora v2.6, released in 9.1 IP1, and contains the following information:
- New Features
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24307).
New Features
- Updated for ISE 9.1i
- File name and module name are appended with core name so that multiple cores can be generated
- make_aurora.pl script is modified to run in Windows platform
- TX_LOCK and RX_LOCK signal brought out to top module to facilitate easy debugging
Known Issues
- Avoid using REFCLK for multilane Virtex-II Pro X designs because problems in MAP and PAR prevent them from working
- Remember to set pin constraints in the "aurora_sample.ucf" file before using the aurora_sample design