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AR# 24601

LogiCORE Endpoint v3.4 and v3.4.1 for PCI Express - Release Notes and Known Issues for 9.1i IP Update 1 (9.1i_IP1) and 9.1i IP Update 2 (9.1i_IP2)


This Release Note and Known Issues Answer Record is for the LogiCORE Endpoint v3.4 for PCI Express released in 9.1i IP Update 1 and 9.1i IP Update 2, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24307).


General Information

Updates for the pci_exp_1_lane_32b_ep, pci_exp_4_lane_32b_ep, and pci_exp_8_lane_64b_ep Cores

IMPORTANT NOTE: 9.1i IP Update 2 is a cumulative IP Update release. However, the LogiCORE Endpoint v3.4 for PCI Express was not updated in IP Update 2. Consequently, the same core exists in both IP Update 1 and IP Update 2. As a result, if you have installed the v3.4.1 patch, you must reinstall it after installing the 9.1i IP Update 2.

A patch update (v3.4.1) is available for the pci_exp_1_lane_32b_ep, pci_exp_4_lane_32b_ep, and pci_exp_8_lane_64b_ep cores. To install this patch, you must first install the 9.1i IP Update 1 or IP Update 2 CORE Generator update; this must be downloaded and installed on top of your current ISE 9.1i SP2 or SP3 design tools. For general information about this update, see (Xilinx Answer 24307). This update is found at:


Once the IP Update has been installed, download the patch at:


To install this v3.4.1 patch update, unzip the file into your current Xilinx install directory as pointed to by your Xilinx environment variable. You might be prompted to allow the update to overwrite existing files; select "Yes to All."

Updates for the pci_exp_1_lane_64b_ep and pci_exp_4_lane_64b_ep Cores

If you are using the pci_exp_1_lane_64b_ep and pci_exp_4_lane_64b_ep, download a new zip file containing this update from the PCI Express Lounge at:


The zip file release is v3.4.1.

Interrupt Interface Changes

The LogiCORE Endpoint for PCI Express v3.4 has an enhanced interrupt interface that supports multivector MSI and multiple legacy interrupt messages. Designs migrated from v3.3 require port changes to the core interface and logic changes to control the new interface. Refer to the User Guide that is delivered with the core for more information on using the new interface.

New Features

- Added multivector MSI

- Legacy Interrupt now supports INTB, INTC and INTD

Bug Fixes

- CR 427097: Core no longer sends spurious "Enter-L1 DLLP" immediately after recovery from L1 to L1

- CR 430740: I/O BAR size can now be selected down to 16 bytes

- CR 431649: Corrected GT11 clock correction settings

- CR 425746: When extended configuration space is enabled, the TLM now allows the user application to transmit in a non-D0 state

Known Issues

- Refer to the "readme_pci_express.txt" file delivered with the core for known issues at the time of the release.

- Known issues discovered post-release will be listed here; check this Answer Record for updates.

AR# 24601
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article