LogiCORE PCI-X v6.2- Release Notes and Known Issues for 9.1i IP Update 1 (9.1i_IP1)
Description
Keywords: CORE Generator, ISE, installation, IP, update, pci
This Release Note and Known Issues Answer Record is for the LogiCORE PCI-X v6.2 released in 9.1i IP Update 1, and contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24307).
Solution
General InformationThe LogiCORE PCI v6.2 supports Virtex-5 and newer architectures only. For all other devices, use the v5.161 PCI-X core. For more information on this core, refer to (Xilinx Answer 24607).
New Features
-Supports ISE 9.1i SP1
-VHDL example design
-Synplicity example design flow
-Virtex-5 XC5VLX50TFF1136-1 support at 133 MHz
Bug Fixes
- CR 418074, CR 418076: Fixed internal errors with MSI Requested Messages and Continue Capability List settings in the customization GUI
- CR422624: Various timing errors fixed
Known Issues
- Please refer to the release notes text file delivered with the core for known issues at the time of the release.
- The v6.2 solution for PCI-X does not support operation up to 133 MHz in a -1 speedgrade. This is caused by the fact the DCM used in the core to meet timing does not accept frequencies over 120 MHz when using the -1 speedgrade. This problem is currently being investigated and a fix is planned for 9.1i IP Update 3 due out in May 2007.