We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24609

LogiCOREPCI/PCI-X UCF Generator v2.2 - Release Notes and Known Issues for 9.1i IP Update 1 (9.1i_IP1)


This Release Note and Known Issues Answer Record is for the LogiCORE PCI/PCI-X UCF Generator v2.2 released in 9.1i IP Update 1, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24307).


General Information

- See (Xilinx Answer 22921) for general information regarding timing closure in Virtex-4 devices.

New Features

-Supports ISE 9.1i SP1.

Bug Fixes

- Removed Spartan-3A support pending further evaluation

- CR 421565: Fixed spurious crashes with Spartan-3E

- CR 421711: Fixed unsupported NODELAY constraint in Virtex-5 UCF files, changed to IOBDELAY = NONE

Known Issues

- Please refer to the release notes text file delivered with the ucf for known issues at the time of the release.

- For Virtex-5 PCI UCFs, the pin location for RCLK_N and RCLK_P is not being specified. You need to select valid pin locations for these pins.

- For Virtex-5 PCI UCFs, the UCF Generator is not setting the correct IOSTANDARD for RCLK_P and RCLK_N. Please see (Xilinx Answer 24863) for more information.

AR# 24609
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article