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AR# 24644

MPMC2 v1.7 - Using multiple instances of MPMC2


Are there any special steps that I must use to have multiple instances of the MPMC2 controller in my design?

In my design, multiple cores use IDELAYCTRL; is there something I must do to get my system to work?


Note: This Answer Record only applies to MPMC2 v1.7. For later MPMC versions, refer to the appropriate documentation:

-MPMC2v1.8/v1.9 - Refer to UG253: "Multi-Port Memory Controller 2 User Guide (MPMC2)."

-MPMC v3.00.a and later Refer to the "Memory Controller Architecture->IDELAY Controller" section of the MPMC data sheet, mpmc.pdf, distributed with EDK.


To have two or more instances of the MPMC2 in your design, you must modify the generated code to work around the use of IDELAYCTRL.

The instantiation of the IDELAYCTRL primitives is not as automatic in the build procedure. You must instantiate the number of IDELAYCTRL primitives for your design and provide LOC constraints for each IDELAYCTRL. This is required for EDK 8.xi tools because when instantiating only one IDELAYCTRL without LOC constraints, the tools replicate the primitive throughout the design. Replicating the primitive has the undesirable results of higher power consumption, utilization of more global clock resources, and greater use of routing resources. To prevent these undesirable results, a procedure is described in the next paragraph for instantiating the IDELAYCTRLs. See the Virtex-4 User Guide discussion of IDELAYCTRL usage and design guidance for more information on IDELAYCTRL. Tools beyond ISE 8.xi might handle IDELAYCTRL instantiation differently. The Virtex-4 User Guide is accessible at:


To avoid the undesirable results noted above, you must modify a portion of the MPMC2 v1.7 RTL code and replicate the instances for the number required. See the Virtex-4 User Guide discussion of IDELAYCTRL usage and design guidance or the Virtex-4 Library Guide for IDELAYCTRL primitives for more details.

When more than one IDELAYCTRL is instantiated, the ISE 8.xi tools require LOC constraints on each IDELAYCTRL instantiation. A failure in MAP occurs if the LOC constraints are not provided. You can use the FPGA Editor to help determine IDELAYCTRL LOC coordinates for your pinout. The syntax for the UCF file LOC constraints is shown in the example below; the instance name in the MPMC2 for each IDELAYCTRL is idelayctrl0 to idelayctrlN, where N is the number of instantiated IDELAYCTRL, less one. You must include only one LOC entry for each instance used in the system design and not for all possible IDELAY controllers. For each entry, include the LOC coordinates for the part and pinout in the design. The example below is for a design that uses two IDELAYCTRL primitives.

Before you modify the code for the IDELAYCTRL, you should ensure that you have identified all of the IDELAYCTRL's used by the MPMC2 core(s).

The example below is for a system with two IDELAYCTRL primitives with example only coordinates. Depending on your pinout, more IDELAYCTRLs might be needed.

Lines required in the UCF file:

INST *idelayctrl0 LOC=IDELAYCTRL_X2Y5;

INST *idelayctrl1 LOC=IDELAYCTRL_X2Y4;

Modified RTL:

<location of MPMC2 pcore>/hdl/verilog/mpmc2_phy_if_ilogic_datapath.v

Starting at line 85 -

IDELAYCTRL idelayctrl0 (





Modified to:

wire idelay_ctrl_rdy0,


IDELAYCTRL idelayctrl0 (





IDELAYCTRL idelayctrl0 (





assign idelay_ctrl_rdy = idelay_ctrl_rdy0 & idelay_ctrl_rdy1;
AR# 24644
Date Created 09/04/2007
Last Updated 11/12/2010
Status Archive
Type General Article