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AR# 24647

MIG v1.6 - Virtex-5 DDR2 SDRAM controller reads in data during DQS post-amble glitch


In DDR/DDR2 SDRAM interfaces, it is possible for "false" clock edges on the DQS strobe to register in the FPGA when DQS becomes three-stated one-half clock cycle after the last falling edge of a read burst (the "read post-amble"). The physical layer of memory controllers are designed not to read in data during the read post-amble. However, the DDR2 SDRAM controller for Virtex-5 does not always avoid reading data during this condition (dependent on frequency, as well as chip- and board-related delays). This might cause the last falling edge data of a read burst to be corrupted.


This problem depends on the condition of the DQS calibration during the glitch and is independent of frequency.

MIG 1.7 resolves this issue as it will avoid the glitch from 140 MHz to 333 MHz.

NOTE: The correct frequency must be set in the code for the calibration logic to properly position the DQS and in turn avoid the glitch.
AR# 24647
Date Created 09/04/2007
Last Updated 02/10/2012
Status Archive
Type General Article