The tcl script sets the clk name for the Offset constraints with the following statement :
set global_pclk_name [get_in_port_connect_global $mhsinst "PCLK"]
When implementing the design with ISE, the following error occurs if the top-level port name connected to PCLK does not match the port of the MHS file.
ERROR:XdmHelpers:678 - Processing TIMESPEC definition
"TSO_PCI_PADS_P_out_fpga_0_PCI_CLK_FB_SLOW_FFS=TIMEGRP PCI_PADS_P OFFSET =
OUT 28000.000000 pS AFTER fpga_0_PCI_CLK_FB TIMEGRP SLOW_FFS" on instance
"fpga_0_PCI_CLK_FB" not found.
In the top-level file, I have the following port map:
fpga_0_PCI_CLK_FB => fpga_0_PCI_CLK, (line 112)
The user has selected ISE implementation flow instead of EDK flow and selects system as sub module. In creating "top.vhd", the user does not keep the PCI clock port name as stated in MHS. This is the reason we see that NGDBuild failure.
Core TCL can only check the system port name from MHS and generate the core UCF accordingly. There is no way core TCL can predict and restrict the user action when the user writes up top-level HDL by himself or herself.
When the ISE flow is selected in the EDK tool with any core that has timing constraints which are generated by tcl-scripts and that are combined with the ngc-file of the core, then errors can occur if the MHS file port names are not propagated up the hierarchy in the user supplied files (mainly top-level) for the ISE flow.
In the context of opb_pci bridge, it is necessary to propagate the pci port names in the mhs-file to the top-level hdl-file. If the names are changed in the user-supplied hdl-files, the PCI constraints, such as offset in or out, will generate errors in NGDBuild because the tool will not find the net name provided by the tcl-script and combined in the opb_pci bridge ngc-file.