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AR# 24657

MPMC2 v1.7 - Data read from the external DDR/DDR2 memory through the MPMC2 is incorrect/corrupt/rotated

Description


When reading from the external memory through the MPMC2, the data is incorrect. Are there any adjustments that can be made to correct the data?



WR at 0x....0 => RD at 0x...8

WR at 0x....4 => RD at 0x...C

WR at 0x....8 => RD at 0x...0

WR at 0x....C => RD at 0x...4

Solution


The Physical Interface (PHY) for the MPMC2 v1.7 in Virtex-4 will automatically align the read data so that the read data will be sampled and pushed into the read data path FIFOs at the appropriate time. The PHY implementation for the MPMC2 v1.7 can adjust the read data by only up to one clock cycle. It is possible that the DDR and DDR2 designs may fall outside of that window because board propagation delays. If the data is received outside of this window, read errors will occur.



Whole Clock Period Adjustment:



The read calibration window can be shifted by a whole clock period by adjusting two parameters found in <generated_pcore_directory>/hdl/verilog/mpmc2_ctrl_path_params.v



-> C_CTRL_Q10_DELAY

-> C_CTRL_DP_RDFIFO_WHICHPORT_DELAY



DDR Design running at 100MHz: Increment these parameters by one (1).

DDR2 Design running at 200MHz: Decrement these parameters by one (1) or more.



As you adjust these parameters from the defaults in the generated code, simulation mismatches can occur. The simulation environment should be modified to reflect the actual board delays or maintain different values for simulation and synthesis.



DDR2 Half Clock Period Adjustment:



Depending on the board layout, the byte lanes may not be exactly matched and the read calibration window may have to be shifted by a half cycle or on the half-cycle boundary. This can be acomplished by the following modifications to <generated_pcore_directory>/hdl/verilog/mpmc2_phy_if.v



NEW< >OLD

Line: 708

< mem_dq_i_tmp_int_d1[i*C_MEM_BITS_DATA_PER_DQS+C_MEM_BITS_DATA_PER_DQS-1:i*C_MEM_BITS_DATA_PER_DQS] :

---

> mem_dq_i_tmp_int[i*C_MEM_BITS_DATA_PER_DQS+C_MEM_BITS_DATA_PER_DQS-1:i*C_MEM_BITS_DATA_PER_DQS] :

Line: 712

< mem_dq_i_tmp_int_d1[i*C_MEM_BITS_DATA_PER_DQS+C_MEM_BITS_DATA_PER_DQS-1+C_MEM_DATA_WIDTH:i*C_MEM_BITS_DATA_PER_DQS+C_MEM_DATA_WIDTH] :

---

> mem_dq_i_tmp_int[i*C_MEM_BITS_DATA_PER_DQS+C_MEM_BITS_DATA_PER_DQS-1+C_MEM_DATA_WIDTH:i*C_MEM_BITS_DATA_PER_DQS+C_MEM_DATA_WIDTH] :



From this point, the read calibration window may still have to be shifted by one or more wholes cycles as described in "Whole Clock Period Adjustment" above.
AR# 24657
Date Created 09/04/2007
Last Updated 11/12/2010
Status Archive
Type General Article