Solution
Control sets are the collection of control signals (Clock, CE and SR) for slice registers and LUTRAM.
Registers must belong to the same control set in order to be packed into the same slice component.
Also, registers with no CE or SR signal cannot be packed into the same slice with registers that do.
As the number of unique control sets increases, it becomes more difficult to fit a device.
This situation can also result in routing congestion which can cause timing degradation or nets that cannot route completely.
Note:
When MAP is run with the "-detail" option, the MAP report (.mrp) will
contain a list of control sets specifying the nets involved in each
set.
For details on Slice connectivity, see the CLB Overview section, "Diagram of SLICEM" (Figure 5-3) of the Virtex-5 User Guide (UG190):
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides
Navigate to FPGA Device Families -> Virtex-5 -> Virtex-5 User Guide.
For example, consider a control set that contains a single flip-flop.
Because
no other register shares the same control set, the register is packed
into a slice containing three unusable flip-flop BELs.
The same holds
true for a control set with 21 flip-flops.
Divide the number of
flip-flops in the set by four, and then subtract the remainder from four
to determine the minimum number of unusable register BELs for the set.
For
the following design summary, which indicates that register utilization
was only 82%, 2867 registers (15%) are unusable and, consequently, the
effective register utilization is actually 97% with optimal packing
results.
This information clearly illustrates that a reduction in the
number of unique control sets is necessary for this design to fit.
Number of Slice Registers: 15,778 out of 19,200 82%
Number used as Flip Flops: 15,583
Number used as Latches: 8
Number used as Latch-thrus: 187
...
Slice Logic Distribution:
Number of occupied Slices: 5,784 out of 4,800 120% (OVERMAPPED)
Number of LUT Flip Flop pairs used: 20,113
Number with an unused Flip Flop: 4,335 out of 20,113 21%
Number with an unused LUT: 6,437 out of 20,113 32%
Number of fully used LUT-FF pairs: 9,341 out of 20,113 46%
Number of unique control sets: 1,127
A future enhancement is planned for the MAP report to print effective register utilization in the Design Summary.
In the meantime, you can run the following Perl script to calculate the number of unusable registers due to control sets.
To run the script, perform the following steps:
1. Create the script file "cset.pl".
2. Modify the first line so that path points to the $XILINX/bin/lin directory, where xilperl is located.
3. Run MAP with the -detail switch.
4. Run the command:
cset.pl design.mrp
--- script starts below ---
#!/path/to/XILINX/install/dir/xilperl
# This script takes an .mrp file run with -detail as input
$set="1";
$total="0";
while (<>){
chomp;
@fields =split();
# Capture Load Count
if ($fields[0] eq "LOAD" && $fields[1] eq "COUNT:") {
$loads=$fields[2];
$remain=$fields[2] % 4;
if ($remain eq "0") {
$unused="0";
}
if ($remain ne "0") {
$unused=4-$remain;
}
print "Set number $set has $loads loads.\n";
print "There are $unused unusable registers in this set.\n";
$total=$total+$unused;
$set++
}
}
print "There are a total of $total unusable registers due to control sets.\n";