In 9.1i design tools and earlier, when using multiple GT11s configured for Low-latency buffered mode with channel deskew, a significant skew of about 20 UI can sometimes be seen between the TX serial pins of different GT11s in timing simulation.
A work-around is currently being investigated for this issue.
To check on the current status of this issue, contact Xilinx technical support at:
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 33302 | LogiCORE IP XAUI v9.1 and v9.1 rev1 - Release Notes and Known Issues for ISE Design Suite 11.3 and 11.5 | N/A | N/A |