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AR# 24678

Virtex-4 GT11 SmartModel Simulation - TX serial output skewed in SimPrims Timing simulation

Description

In 9.1i design tools and earlier, when using multiple GT11s configured for Low-latency buffered mode with channel deskew, a significant skew of about 20 UI can sometimes be seen between the TX serial pins of different GT11s in timing simulation.

Solution

A work-around is currently being investigated for this issue.  

 

To check on the current status of this issue, contact Xilinx technical support at:  

http://www.xilinx.com/support/techsup/tappinfo.htm.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33302 LogiCORE IP XAUI v9.1 and v9.1 rev1 - Release Notes and Known Issues for ISE Design Suite 11.3 and 11.5 N/A N/A
AR# 24678
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article