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AR# 24697

LogiCORE Endpoint Block Plus for PCI Express v1.5 - Does the v1.5 Block Plus Core support Virtex-5 engineering sample (ES) silicon? Does the Core support ML555 and ML505/ML506 boards that have ES silicon?


Can the LogiCORE Endpoint Block Plus for PCI Express v1.5 be used on other ES silicon devices or pin-outs?  


Can the LogiCORE Endpoint Block Plus for PCI Express v1.5 be used with the ML555 and ML505/ML506 boards containing ES (Engineering Samples) silicon?


Xilinx strongly recommends that you target production Virtex-5 devices and the LogiCORE Endpoint Block Plus for PCIe when targeting the Integrated PCI Express block. 

Known issues in Virtex-5 ES silicon are listed in the errata: 


These known issues might impede performance and functionality when using the Block Plus Core for PCI Express as discussed in (Xilinx Answer 25032).  


ES silicon is not warranted for production release usage, and Xilinx LogiCORE devices used in ES silicon are not warranted for production release usage. 


What are the known issues when targeting Virtex-5 ES silicon for PCI Express? 


Refer to (Xilinx Answer 25032)


Is there a new patch for the v1.6.1 core released in ISE 10.1 Initial IP Update? 


No, the last Block Plus core version with ES silicon support is v1.5 with the EA patch installed. 


What is the LogiCORE Endpoint Block Plus v1.5 for PCI Express EA patch? 


The EA patch provides support for certain ES devices, as shown in the table below. 


Can the LogiCORE Endpoint Block Plus v1.5 for PCI Express EA patch be used with the v1.5.2 or v1.5.1 production patch release? 


No. This patch can be used only on the standard v1.5 Block Plus core install that comes in 9.2i IP Update 2. 


What is the LogiCORE Endpoint Block Plus v1.5 for PCI Express EA UCF ZIP file, and where can it be found? 


The EA UCF patch contains the UCFs required to support the ES devices, as shown in the table below. 

These UCFs should be placed in the example_directory generated by the CORE Generator. 

The "implement.bat" or "implement.sh" file found in the implement directory should be updated to point to these UCFs during implementation. 


The UCF files can be downloaded at: 


How do I install the patch? 


Use the following steps to install the Block Plus Core EA patch for Virtex-5 ES silicon: 


1. Install 9.2i SP2 IP Update 2. 

The IP Update is available from:  


2. Download the EA patch from: 


3. Unzip the "pcie_block_plus_v1_5_92i_ip_update_2_ea.zip" archive to your Xilinx installation directory as pointed to by your Xilinx path variable.

You are prompted to overwrite existing files.

Select "Yes to All" and allow it to overwrite these files. 


Can I target production silicon after the patch is installed? 


No, you cannot target production Virtex-5 silicon with the EA patch installed. 

To remove the patch, follow these instructions: 


1. Download this archive from: 


2. Unzip the "pcie_block_plus_v1_5_92i_ip_update_2_prod.zip" archive to your Xilinx installation directory as pointed to by your Xilinx path variable.

You are prompted to overwrite existing files. 

Select "Yes to All" and allow it to overwrite these files. 


Which Virtex-5 ES devices are supported? 


The following table displays which ES devices are supported and indicates whether the patch is required. 




Are the GTP locations provided in the UCF EA patch ZIP equivalent to the GTP locations for production Virtex-5 silicon provided with the v1.5 Block Plus Core? 


No. ES silicon requires different GTP locations in some cases because of the difficulty in meeting timing on the interface between the integrated block for PCI Express and the GTPs. 

Production devices allow for more board-friendly GTP locations, which is why the UCFs generated by CORE Generator have different locations.  


Will the ES UCF GTP locations also be supported in production silicon? 


Yes. Users are not required to redesign boards when moving from ES silicon to production silicon.

The ES pin-outs will be supported on production devices. 


How can I verify that the EA patch is installed correctly? 


Once installed, the EA patch changes the release notes file "pcie_blk_plus_release_notes.txt" to include the following in the revision history: 


Date By Version Description 


02/2007 Xilinx, Inc. 1.2 9.1i SP2 - IP Update 1 

03/2007 Xilinx, Inc. 1.2 rev 1 Update for rev 1 patch 

05/2007 Xilinx, Inc. 1.3 9.1i SP3 - IP Update 3 

08/2007 Xilinx, Inc. 1.4 9.2i SP2 - IP Update 1 

10/2007 Xilinx, Inc. 1.5 9.2i SP3 - IP Update 2 

10/2007 Xilinx, Inc. 1.5 EA Add support for V5 SXT/LXT ES devices 



Also, once installed and PCI Endpoint Block Plus 1.5 is highlighted in the CORE Generator taxonomy list, the right panel indicates "EA": 




What is the purpose of the EA patch? 


Virtex-5 ES silicon requires that the Integrated Block for the PCI Express RESETMODE attribute be set to FALSE, while in production it is set to TRUE. 

These devices also require that the GTP TXUSERCLK inputs be inverted to address hold time issues on the Integrated Block to GTP interface. 

The EA patch overlays two source files into the CORE Generator install, allowing CORE Generator to produce a netlist that works on the ES devices. 


What about other ES devices not listed in the table above? 


This solution will soon be updated with information on supporting these devices with the Block Plus Core. 

Refer back to this Answer Record or, if you need immediate help, open a WebCase and reference this Answer Record at:  


How do I target ML555 or ML505 boards? 


For ML555 and ML505 boards containing ES silicon, follow the instructions above to install the EA patch.  



The XC5VLX50T-1FF1136CES and XC5VLX110T-1FF1136CES included with the "pcie_block_plus_ea_ucf.zip" archive contain the correct GTP locations and placements for the ML555 boards with ES silicon.  


ML505 and ML506 

The ML505 and ML506 uses GTP location X0Y1 for the single lane interface. 

Use the "Xilinx_pci_exp_blk_plus_1_lane_ep-XC5VLX50T-FF1136-1_ES.ucf" file (ML505) or "Xilinx_pci_exp_blk_plus_1_lane_ep-XC5VSX50T-FF1136-1_ES.ucf" file (ML506) from the UCF zip archive and change the GTP location to: 


INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_gt_wrapper_i/GTPD[0].GTP_i" LOC = GTP_DUAL_X0Y1 ; 


The reset and clock constraint locations for this board are as follows: 


NET "sys_reset_n" LOC = "AC24" | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ; 

NET "sys_clk_p" LOC = "AF4" ; 

NET "sys_clk_n" LOC = "AF3" ; 



Archived Patches 


v1.4 Rev 2 EA 


Patch: http://www.xilinx.com/txpatches/pub/swhelp/coregen/pcie_bp_v1_4_2_92i_ip_update_1_ea.zip
Reversal Patch: http://www.xilinx.com/txpatches/pub/swhelp/coregen/pcie_bp_v1_4_2_92i_ip_update_1_prod.zip

v1.4 Rev 1 EA 

This patch has been removed from the FTP site because of a problem in the patch. 

The v1.4.2 EA patch replaces v1.4.1 EA and should be used instead. 


v1.4 EA 

For customers looking for the v1.4 EA patch, it can still be accessed. 

However, users should always use the v1.4.2 patch instead.

The v1.4.2 patch fixes a critical issue described in (Xilinx Answer 29287)


Patch: http://www.xilinx.com/txpatches/pub/swhelp/coregen/pcie_block_plus_v1_4_92i_ip_update_1_ea.zip

Reversal Patch: http://www.xilinx.com/txpatches/pub/swhelp/coregen/pcie_block_plus_v1_4_92i_ip_update_1_prod.zip

v1.3 EA 

Patch: http://www.xilinx.com/txpatches/pub/swhelp/coregen/pci_express_91i_ip_rel_3_rev1_ea.zip
Reversal Patch: Not Available 


v1.2.1 EA 

Patch: http://www.xilinx.com/txpatches/pub/applications/pci/pci_express_91i_rev1_ea.zip
Reversal Patch: Not Available 



Revision History 

09/11/2008 - Updated to inform that ES is not supported with v1.5.1 

03/07/2008 - Added SX50T UCF reference for ML506. Added note regarding v1.5.2.

AR# 24697
Date Created 09/04/2007
Last Updated 06/10/2015
Status Active
Type General Article
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Endpoint Block Plus Wrapper for PCI Express
Boards & Kits
  • ML555
  • ML505
  • ML506