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AR# 24704

Virtex-6/-5/-4 - Finding IDELAYCTRL locations

Description

The Virtex-4 FPGA User Guide (UG070) indicates IDELAYCTRL can be instantiated with or without location (LOC) constraints.

When the IDELAYCTRL is instantiated with location constraints (e.g., "INST .idelayctrl_instance_name. LOC = IDELAYCTRL_XnYm"), how can the location coordinates of it be determined?

Solution

An IDELAYCTRL module exists in an I/O column in every clock region. An IDELAYCTRL module calibrates all the IDELAY modules within its I/O Bank.

The exact location coordinates of an IDELAYCTRL can also be found in the PlanAhead tool. Following is a set of detailed steps on how to find IDELAYCTRLs in the PlanAhead tool:

1. Open a design in thePlanAhead tool.
2. In the package view, click on the desired pin.
3. In the device view, zoom in on the area of the highlighted pin.
4. Scroll the pointer over the IDELAYCTRL (located on the left side of the nearest red box; see picture).

I/O Banks
I/O Banks


The location of the controller is shown in the "fly by" text (see picture below).

IDELAYCTRL Location
IDELAYCTRL Location


The exact location coordinates of an IDELAYCTRL can also be found in FPGA Editor. Following is a set of detailed steps on how to find IDELAYCTRLs in the FPGA Editor.

1. Open a design in the ISE design tool.
2. Invoke FPGA Editor by selecting "Implement Design -> Place & Route -> View/Edit Routed Design (FPGA Editor)" or "Implement Design -> Map -> Manually Place & Route (FPGA Editor)."
3. In FPGA Editor, select Edit -> Find.
4. Find what = "Site"; Name = "IDELAYCTRL*."
5. World window will highlight the location of IDELAYCTRL's.
6. Zoom in and check the name of this IDELAYCTRL.

IOBs classified by Clock Region can be viewed in PACE by selecting "IOBs -> Show Clock Regions."

Using FPGA Editor and PACE together helps to determine which IDELAYCTRL should be used and the location coordinates of it.

Some Xilinx customers prefer to use an outside tool (ADEPT) to generate this location information:
https://sites.google.com/site/adepthome/

NOTE: This tool is not supported by Xilinx.

AR# 24704
Date Created 05/20/2008
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • More
  • Virtex-4 SX
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • PlanAhead - 10.1
  • PlanAhead - 10.1 sp1
  • PlanAhead - 10.1 sp2
  • More
  • PlanAhead - 10.1 sp3
  • PlanAhead - 11.1
  • PlanAhead - 11.2
  • PlanAhead - 12.1
  • PlanAhead - 12.2
  • PlanAhead - 12.3
  • Less