UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24712

LogiCORE Block Memory Generator and FIFO Generator Core - How to test user logic that triggers ECC SBITERR and DBITERR outputs

Description

This Answer Record describes how to test user logic that triggers on the SBITERR and DBITERR outputs associated with the ECC feature enabled in the Block Memory Generator and FIFO Generator cores.

Solution


Insertion of SBITERR and DBITERR errors must be done external to the core using additional test logic.
To test user logic that triggers on SBITERR and DBITERR, additional logic needs to be combined with SBITERR or DBITERR output of the core. For an example for testing SBITERR,see the following diagram.


SBITERR/DBITERR Insertion
SBITERR/DBITERR Insertion



You can force the insertion of a SBITERR signal into the design to exercise the user logic that triggers on this error signal by asserting the FORCE_SBITERR signal. Using a MUX to control the source of the SBITERR lets you synthesize this logic only when in debug mode.
AR# 24712
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • FIFO Generator
  • Block Memory Generator