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AR# 24713

MIG - Is it possible to generate a design for Mobile SDRAM?


MIG currently does not include support for Mobile SDRAM for Virtex-4, VIrtex-5, Virtex-6 or Spartan-3 Generation.

Is there a plan to add support in the near future, or is there a way to modify a MIG output to add support?


The Spartan-6 MCB supports Mobile SDRAM.

There is currently no plan to add support for Mobile SDRAM to any other architecture. If the target architecture is Virtex-4/-5, it might be possible to port the Spartan-3 SDRAM design to the target FPGA device.

The DDR/DDR2 SDRAM design for the Spartan-3 architectures match more closely what is needed for Mobile SDRAM than the Virtex-4/-5 design. The data capture will most likely have to go directly to a FIFO, and it is important that the write enables to the FIFO have a full clock cycle to be able to absorb the variations of the memory. Both of these features are a part of the Spartan-3 design. However, this has not been analyzed or tested, so full verification is required.

The direct clocking technique used in the DDR/DDR2 SDRAM design for Virtex-4 is not the best match for this technology as the variation of the DQ lines, with respect to the input clock, is quite high compared to standard DDR. This is because Mobile DDR parts do not have the DLL that is present in other DDR SDRAM parts. The lack of the DLL changes the timing of the memory substantially and has a much larger variation. This variation is not split up by process, voltage, and temperature on the data sheet. Also, be aware that the I/O voltage is not the same as standard DDR.

If a fully verified design is required, contact Xilinx Design Services at:


Alternatively, you can contact the Xilinx Alliance Partner: Northwest Logic.

AR# 24713
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article