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AR# 24719

LogiCORE XAUI v7.0 - Changes needed for Virtex-5 GTP TX initialization block

Description

In GTP TX Buffer Bypass mode, you need to ensure that the tx_sync block provided by the GTP Wizard is held in reset until there is a stable clock, and the GTP PLL has locked in both tiles. Currently the tx_sync block is held in reset only until a stable clock is present. The resulting impact is that the phase alignment procedure can be incorrect leading to incorrect output data from any GTP. Also, previously, Virtex-5 RocketIO Phase-Alignment circuit would set TXENPHASEALIGN Low after phase alignment was completed. This signal should remain High.

Solution

For Verilog 

 

In <xaui_core_name>_block.v change line 410 From: 

.RESET(reset156), 

To: 

.RESET(reset156 || ~lock), 

 

In rocketio_init_tx.v change line 111 From: 

assign TXENPMAPHASEALIGN = wait_stable_r | phase_align_r; 

 

To: 

assign TXENPMAPHASEALIGN = !begin_r; 

 

 

 

For VHDL 

 

In <xaui_core_name>_block.vhd change line 661 From: 

RESET => reset156, 

To: 

RESET => rocketio_init_tx_reset, 

 

and add: 

signal rocketio_init_tx_reset :std_logic; 

rocketio_init_tx_reset <= (reset156 or (not lock));  

 

In rocketio_init_tx.vhd change line 130 From: 

TXENPMAPHASEALIGN <= wait_stable_r or phase_align_r; 

 

TO: 

TXENPMAPHASEALIGN <= not begin_r;

AR# 24719
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article