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AR# 24724

9.1i Architecture Wizard - ERROR:PhysDesignRules:1443 - Dangling pins on block:


The Architecture Wizard generates incorrect VHDL and Verilog for the PLL2DCM configuration. The HDL generated for PLL2DCM with default values contains:

// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUTDCM0 = 0.420 ns



Note: The CLKINSEL is left unconnected. This results in the following error:

ERROR:PhysDesignRules:1443 - Dangling pins on block:<instance_name/PLL_ADV_INST/instance_name/PLL_ADV_INST>:<PLL_ADV_PLL_ADV>. The PLL_ADV input pins CLKIN1 and CLKINSEL must have a connection.

ERROR:PhysDesignRules:10 - The network <instance_name/CLKOUTDCM0_CLKIN> is completely unrouted.

ERROR:Bitgen:25 - DRC detected 2 errors and 0 warnings.

ERROR (dpm_flowUtilsExec): bitgen failed


This issue will be resolved in a future software release. Until this issue is addressed, the code must be updated manually.

AR# 24724
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article