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AR# 24727

9.1 XST - XST misinterprets relative PERIOD constraint which results in incorrect timing analysis

Description

If a PERIOD is defined in MHz and another period is specified as a multiple of the original period, XST misinterprets the constraint, dividing instead of multiplying. This issue is causing poor utilization in the PCIE designs for V5 LXT/SXT. 

 

For example: 

 

XST always multiplys the "period" for related clock constraint instead of looking at the original unit of the primary constraint. 

 

TIMESPEC TS1 = PERIOD clk1 250MHz; 

TIMESPEC TS2 = PERIOD clk2 TS1 * 2; 

 

XST sees TS1 as 4 ns and TS2 as 8 ns. This results in clk2 being optimized at 125MHz, which is incorrect.

Solution

This issue has been addressed in ISE 9.1i Service Pack 2. Until this issue has been addressed, each individual TIMESPEC should be assigned and individual specification which is independent of others.

AR# 24727
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article