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AR# 24750

9.1i EDK FSL_V20 v2.00a - Allow block RAM-based FIFO in the FSL component

Description

Change the FSL_V20 v2.00a component to allow the coincident setting of the parameters C_ASYNC_CLKS = 1 and C_IMPL_STYLE = 1. 

 

This combination provides a block RAM-based Async FIFO inside the FSL_V20 component and provides the following benefits: 

 

- deeper asynchronous FIFOs in an FSL 

- less challenging routing requirements since the SRLs are avoided

Solution

The block RAM implementation of FIFO is completed in EDK 9.1i, available at: 

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

AR# 24750
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article