VCS, SmartModel/SWIFT Interface - How do I use the MGT and PPC 64-bit SmartModels in VCS?
Description
Keywords: Simulation, GT, GTP_DUAL,Synopsys RocketIO, serial, transceiver, EMAC, fibre, channel, gigabit, Ethernet, XAUI, SmartModel
The Hard IP simulation flow uses Synopsys VMC models to simulate the IBM PowerPC microprocessor and RocketIO multi-gigabit transceiver. Since VMC models are simulator-independent models derived from the actual design, they are accurate evaluation models. To simulate these models, you must use a simulator that supports the SWIFT interface.
Starting with ISE 9.1i, Xilinx has 64-bit SmartModel Support.
How are these models used in VCS?
Solution
Xilinx recommends using 32-bit simulation unless a 64-bit simulation is needed because of memory space limitations. We have traditionally seen that simulation performance is slower in a 64-bit simulator.When Using VCS-MX on Linux 64, VCS-MX X2006.06 or newer should be used.
Run compxlib to precompile libraries when running VHDL simulation.
Information on compxlib can be found in the software manuals at http://www.xilinx.com/support/documentation/dt_ise.htm
setup file - A description of variables that must be set for correct simulation.
For example:
setenv XILINX <Xilinx path>
setenv VCS_HOME <VCS path>
setenv LM_LICENSE_FILE <license.dat>:${LM_LICENSE_FILE}
setenv VCS_SWIFT_NOTES 1
setenv LMC_HOME $XILINX/smartmodel/lin64/installed_lin64
setenv LMC_CONFIG $LMC_HOME/data/amd64.lmc
setenv VCS_CC gcc
setenv LD_LIBRARY_PATH $LMC_HOME/sim/pli/src:$LMC_HOME/lib/amd64.lib:$LD_LIBRARY_PATH
setenv PATH ${LMC_HOME}/bin :${VCS_HOME}/amd64/bin: ${VCS_HOME}/bin:${PATH}
setenv PATH ${XILINX}/bin/lin64 ${PATH}
Please change the parameters included within the "< >" to match your system configuration.
simulate file - An example VCS compilation simulation script that illustrates which files must be compiled and loaded for simulation. You can modify this file to simulate a design by including the design and testbench files appropriately.
For example:
vcs -lmc-swift -full64\
<design>.v <testbench>.v \
${XILINX}/verilog/src/glbl.v \
-y ${XILINX}/verilog/src/unisims +libext+.v \
-y ${XILINX}/verilog/src/simprims +libext+.v \
-y ${XILINX}/smartmodel/lin/wrappers/vcsmxverilog +libext+.v \
sim -l vcs.log
Please change the parameters included within "< >" to match your design files and testbench.
After you have updated each of these files, you can run the simulation.