This Answer Record shows how to migrate the SPI-4.2 Core from v6.3 to v8.3, and describes the signal changes made to the core. Every attempt was made to keep constraints, input, and output signals consistent between versions.
NOTE: SPI-4.2 v6.x series supports Virtex-II and Virtex-II Pro series, and SPI-4.2 v8.x series supports Virtex-4 and Virtex-5 only. This Answer Record covers the modifications required to upgrade from v6.3 to v8.3.
The following sections are included:
- Core Signal Changes
- Wrapper File Changes
- UCF and NCF File Changes
Core Signal Changes
The following signals were removed from the v8.3 Sink Core:
- SnkDPAMode(Output): Removed in v8.3, not used in the new dynamic alignment configuration.
- SnkDPAModeSel(Input): Removed in v8.3, not used in the new dynamic alignment configuration.
- RDClk180_GP(Output): Removed in v8.3, not used by the core.
The following signals were removed from the v8.3 Source Core:
- SysClk180_GP(Output): Removed in v8.3, not used by the core.
- SysClk180_GBSLV(Input): Removed in v8.3, not used by the Source Core in slave clocking mode.
The following signals were added to the v8.3 Sink Core:
- SnkIdelayRefClk(Input): A 200 MHz reference clock required by the ISERDES. This input signal must be connected to internal or external clock of 200 MHz for both static and dynamic alignment solutions.
- SnkClksRdy(Output): This signal indicates all Sink Core clocks are ready for use. This signal should be monitored during the start-up sequence.
- SnkDPAFailed(Output): Applicable to DPA only. This signal indicates phase alignment has failed at the end of the alignment sequence. This signal should also be monitored during the start-up sequence.
- SnkDPARamAddr (output): Phase Alignment RAM Address. Bus indicating the ISERDES tap value that corresponds to the data on SnkDPARamData.
- SnkDPARamData (output): Phase Alignment RAM Data. Initial data is collected during alignment. It is used to find the valid data window for each bit of the SPI-4.2 bus.
- SnkDPARamValid (output): Phase Alignment RAM Valid. Active High signal indicating the information on SnkDPARamData and SnkDPARamAddr is valid.
The above last three ports present you with the data collected by the logic while finding the data valid window for each of the SPI-4.2 data and control bits (between assertion of PhaseAlignRequest to PhaseAlignComplete). See the User Guide for further information on debugging and the DPA Status Monitoring Feature. These three ports are used solely for debugging purposes. If not needed, you can leave these ports unconnected.
The following signal was added to the v8.3 Source Core:
- SrcClksRdy(Output): This signal indicates all Source Core clocks are ready for use. This signal should be monitored during the start-up sequence.
- DcmLost_TDClk(Output): This signal indicates whether the SysClk_P(N) input is lost and is only available when global clock distribution is used. If it is not needed, it can be left unconnected.
- DcmLost_TSClk(Output): This signal indicates whether the TSClk input is lost. Only available when global clock distribution is used. If not needed, it can be left unconnected.
- SrcOofOverride(Input): When this signal is asserted, the Source core behaves as if in-frame, and sends data on TDat regardless of the status received on TStat. This signal is used for system testing and debugging.
- SrcStatFrameErr (output): Source Status Frame Error: When this signal is asserted (active high), it indicates that a non "11" frame word was received after DIP2 on TStat. This signal is asserted for one clock cycle each time a frame word error is detected. If not needed, you can leave this port unconnected.
For more information, see the SPI-4.2 User Guide.
Wrapper File Changes
The v8.3 wrapper file replaces the v6.3 wrapper file.
NCF File Changes
The v8.3 Core does NOT require NCF files. The v6.3 NCF files must be removed.
UCF File Changes
The UCF file must be updated by replacing all SPI-4.2 constraints in the UCF file with SPI-4.2 constraints provided in the v8.3 release (use the v8.3 UCF files instead of the v6.3 UCF files).
Dynamic Alignment Implementation Considerations
The v8.3 Core has a different dynamic alignment algorithm. For more information on dynamic alignment implementation considerations, see the SPI-4.2 User Guide.