UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24823

9.1i XST - "FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.17"

Description


While running synthesis on the design, I receive the following fatal error:



"FATAL_ERROR:Xst:Portability/export/Port_Main.h:<numbers>"



Why does this occur?

Solution


Xilinx is actively trying to provide better error messages to help you debug the issue. Xilinx recommends that you open a webcase at:

http://www.xilinx.com/support/clearexpress/websupport.htm
and provide a test case that reproduces the problem so that it can be fixed in a future release.



Case 1:

This problem might occur when instantiating IBUF/OBUF/IOBUF in submodules. IBUF/OBUF/IOBUF must be instantiated in the top level of the design.







Case 2:

This might occur when FMAP is being instantiated. You can work around the problem by removing FMAP.







Case 3:

This might occur at the "Advanced HDL Synthesis" step when using dynamic addresses:

reg [15:0] registers [0:7]

assign o_rdata[15:8] = (i_cs & !i_nrw & i_ben[1]) ? registers[i_addr[3:1]][15:8] : 8'h00;"



You can work around the problem by replacing the output assignments o_rdata[15:8] and o_rdata[7:0] with temporary wires. Also, please set the "-signal_encoding" option to "user":

wire [7:0] temp1, temp2;

assign o_rdata[15:8] = temp1;

assign o_rdata[7:0] = temp2;

assign temp1 = (i_cs & !i_nrw & i_ben[1]) ? registers[i_addr[3:1]][15:8] : 8'h00;

assign temp2 = (i_cs & !i_nrw & i_ben[0]) ? registers[i_addr[3:1]][7:0] : 8'h00;







Case 4:

This might occur when XST property "Safe Implementation" is set to "No." To work around the problem, set "Safe Implementation" to "Yes."





Case 5:

To work around the problem, try setting "-signal_encoding" to "user" in Other XST Command Line Options.





Case 6:

This error might occur if there are multiple Asynchronous resets.



For example:

always @(posedge CLK or negedge RESETn or negedge reset_)



Workaround:

always @(posedge CLK or posedge tmp )

where tmp is an intermediate wire, implementing the expected logic
AR# 24823
Date Created 09/04/2007
Last Updated 03/27/2012
Status Archive
Type General Article