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AR# 24826

LogiCORE Endpoint Block and Block Plus for PCI Express - PCI Express interface on ML505 board is not recognized in system and causes OS to hang


Keywords: PCIe, PCI Express

Inserting the ML505 board into a PCI Express slot causes OS to hang and the ML505 board is not detected in the BIOS list of devices.



The ML505 reference design has two reset inputs that are tied to a GPIO DIP (SW8). Bit 8 of SW8 resets the LogiCORE Endpoint Block for PCI Express while bit 7 resets the GTP_DUAL_TILE.

This issue occurs when bit 8 of DIP switch SW8 (in lower right-hand corner of board) is set to zero holding the reference design in reset. Bit 8 is connected to pin AC24 of the Virtex-5 LXT (XC5VLX50T) device. Since the design and integrated block for PCI Express is being held in reset, the OS will not recognize the card. In some systems, this is causing the OS to hang because the system recognizes that a card is in the slot, but cannot communicate with it due to the block being held in reset.

Check to see if DIP switch SW8, bit 8 is set to "0". If this is the case, then set it to "1".

A simple check for this would be to probe the TX/RX signals of the PCI Express link, The RX signals will be toggling correctly, however, no output on the TX signals will be present. Also, capture the reset outputs of the reference design to verify that it is not being held in reset.



Bit 8 of DIP switch SW8 on the ML505 board is connected to pin AC24 of the XC5VLX50T device. This input is acting as a system reset for the whole reference design. By default, this bit is set to "0", causing the device to remain in a state of perminent reset for the reference design.

By doing this, it is ensuring that the card is present within the slot of the PCIe motherboard, and is being detected due to the PRNST1# and PRNST2# signals. However, it is not allowing the BIOS and OS to detect the card within the system, and thus, it is not configuring the card or initiating training sequences. As a result, the OS will hang at the loading stage where it would normally configure all the devices in the PCIe and PCI hierarchy within its system.

To resolve the issue, set bit 8 of DIP switch SW to "1"; the ML505 should now be detected within the system.

A simple check for this would be to inspect the signal on the TX and RX pins of the PCIe link. The RX pins should be receiving valid TS1/TS2 order sets, however, the TX signal will not be responding.
AR# 24826
Date 03/06/2007
Status Active
Type General Article
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