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AR# 24859

9.1i ISE - In Project Navigator, source hierarchy is lost when using synthesis directives


Keywords: Verilog, HDL, meta, comment

In ISE 9.1i, the hierarchy is built incorrectly when synthesis attributes are used.


The hierarchy breaks when the following is used:
// synthesis (example) = 1
// synthesis syn_noclockbuf = 1


There is a problem with the Verilog parser in Project Navigator that causes this problem. The issue is resolved in ISE 9.2i, scheduled for release in June 2007.

To work around the problem in ISE 9.1i, synthesis directives can be written as Verillog-2001 comments or the word attribute can be added to the directive.


The hierarchy is written correctly when the following is used:
// synthesis attribute (example) = 1
// synthesis attribute syn_noclockbuf = 1

or use the following method:

Verilog-2001 Method

(* (example) = 1 *) ;
(* syn_noclockbuf = 1 *) ;
AR# 24859
Date Created 09/04/2007
Last Updated 04/17/2009
Status Archive
Type General Article