Simulating a LogiCORE Endpoint Block v1.2 or v1.1 or Block Plus v1.1 core generated by 8.2i IP Update 3 with 9.1i SmartModels will have simulation problems. This is due to a new input pin, LLKRXDSTCONTREQN, added to the Integrated Block SmartModel for PCI Express in the 9.1i software release. In the 8.2i IP Update 3 cores, this pin was not used and therefore would be floating if simulated with 9.1i SmartModels causing simulations to fail.
To fix this issue, generate a new core using 9.1i SP2 IP Update 1. The LogiCORE Endpoint Block v1.3 or Block Plus v1.2 correctly connects this pin in the design so that the Integrated Block SmartModel for PCI Express will see a valid input value on the pin.