We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24888

LogiCORE RapidIO v4.1 - Migrating from v3.1 to v4.1 (Migration Guide)


This Answer Record provides information on the updates in v4.1 of the Serial Rapid I/O Core. Design changes should be made accordingly when migrating from v3.1 to v4.1.


XCO File and GUI Changes 


Serial Rapid IO solution: End Point Design, Physical Layer and Logical/Transport Layer is merged into one IP. Consequently, the XCO files from the v3.1 core cannot be used to generate the v4.1 core. You must use the v4.1 customization GUI to re-define the desired parameter settings to generate the core. 


Physical Layer 


The MGTs were extracted and an additional level of hierarchy was added to accommodate this change. There is now a phy_wrapper file that incorporates the PHY LogiCore and the external MGT instantiations. 


Logical Layer 


- The tresp port includes an additional input signal, tresp_no_data. When asserted, packet contains no data and consists of header fields only; only valid for reserved types. If not used, tie it to logic "0". See the User Guide for more information. 

- The IReq port is only active when the master_enable bit is set. 

- You no longer need to assert ready to the TREQ or IRESP port prior to receiving the first beat of a transaction.  

- If you are using a 16-bit device ID, the following signals have changed from 8-bit to 16-bit: 

...output [0 : 15] iresp_src_id_o 

...output [0 : 15] iresp_dest_id_o 

...output [0 : 15] treq_dest_id_o 

...input [0 : 15] ireq_dest_id_i 

...output [0 : 15] mreq_src_id_o 

...output [0 : 15] treq_src_id_o 


Design Environment 


- There is now a rio_wrapper.v file in the example_design directory. This file is provided as a design example and instantiates physical layer, logical layer, and buffer module. This file can be used as a template instead of instantiating all thee modules separately.  

- There are no longer multiple directories for supporting PHY and logical layer files. All supporting files have been moved under a global <Component_name> directory:  

-- Clock Modules can now be found with the example_design  

-- Black Box modules are no longer provided; the simulation modules should be useable as synthesis black-boxes 

-- <component>_def.v files previously found in the logical layer and PHY layer template directories are no longer necessary 

-- PHY and logical layer User Guides and Data Sheets can now be found in the centralized doc directory 

- PHY and logical layer .ngc and .v files are no longer in the top-level project directory; they are now in the <Component_name> directory under the project directory 

- In the example_design directory, there is now a "user" directory, which includes an enhanced user design that allows sourcing of traffic when the design is implemented and loaded onto an appropriate ML board (see the Getting Started Guide for more information) 


UCF File Changes 


Review the new UCF file generated in the <comp_name>/example_design/ directory and replace the old constraints with the new constraints.

AR# 24888
Date Created 09/04/2007
Last Updated 05/21/2014
Status Archive
Type General Article