When using IEEE802 Viterbi decoder, I find that a small (1/2LSB) DC offset in the data input can result in BER degradation, or with larger DC offsets the Viterbi decoder might fail to decode input data entirely.
To resolve this issue, follow these steps:
1. Remove DC bias in the soft input data before entering the data into the Viterbi decoder.
2. Use symmetric rounding when the soft data width is larger than the Viterbi input data width. Note that the Viterbi input format is a balanced number system, while the 2s complement number system is unbalanced with one more negative number than positive number, which can lead to 1/2LSB DC offset if mapping does not take this into consideration.
3. If it is not possible to remove DC bias, then increase the width of the path metric state variables. This step ensures that the good path does not saturate and make it indistinguishable from the bad paths in the Viterbi Trellis. Note that the Normalization output activity will now increase due to the input DC offset, even though the data link SNR has not changed. This DC offset impact on Normalization rate should be factored into the synchronization thresholds.