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AR# 24937

LogiCORE FIFO Generator v3.3 - Programmable Full flag remains asserted before any writes to the FIFO occur

Description

When using Independent Clocks, Block RAM FIFO type, the Programmable Full flag asserts and remains asserted when using one of the "Programmable Full Threshold Constant" options. This happens even before any writes to the FIFO occur, and the flag stays asserted regardless of number of reads from the FIFO.

Solution

This issue occurs because of incorrect minimum threshold allowed in the GUI for the "Full Threshold Constant", for example, with the following core options:

Independent Clocks BlockRAM

Write Width: 8

Write Depth: 128

Read Width: 64

Read Depth: 16

First Word Fall Through (FWFT) selected

Programmable Full Flag selected - Single Threshold Constant type

Full Threshold Assert Value = 16

In this case, the depth aspect ratio is "8:1" from write to read, and due to the nature of the FIFO design, the actual minimum Assert value should be 18. However, the GUI allows a Threshold Assert value between 10 and 112 words, which is incorrect.

NOTE: Aspect ratio is calculated based on write_depth to read_depth (input_depth to output_depth).

Example 1: write_depth=128, read_depth=16, would have aspect ratio of 8:1.

Example 2: write_depth=32, read_depth=128, would have aspect ratio of 1:4

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To avoid this Programmable Full flag problem, please use minimum threshold value based on this table.

Following are the minimum programmable full threshold values that are valid to use.

1. For FIFO core configured with Independent Clock Block RAM configuration in standard read mode (no First-Word-Fall-Through):

* Single Programmable Full Threshold Constant configuration:

Write depth:read depth (ratio).....Min threshold value

1:8 ...................................................... 1

1:4 ...................................................... 1

1:2 ...................................................... 1

1:1 ...................................................... 1

2:1 ...................................................... 1

4:1 ...................................................... 1

8:1 ...................................................... 1

* Multiple Programmable Full Threshold Constant configuration:

Aspect Ratio......Min assert threshold value.............Min negate threshold value (prog_full_negate_min)

1:8 ......................................... 2 ............................................................. 1

1:4 ......................................... 2 ............................................................. 1

1:2 ......................................... 2 ............................................................. 1

1:1 ......................................... 2 ............................................................. 1

2:1 ......................................... 2 ............................................................. 1

4:1 ......................................... 2 ............................................................. 1

8:1 ......................................... 2 ............................................................. 1

Rule:

prog_full_negate_min <= prog_full_negate_value < prog_full_assert_val

2. For FIFO core configured with Independent Clock Block RAM configuration in First-Word-Fall-Through read mode:

* Single Programmable Full Threshold Constant configuration:

Aspect Ratio......................Min threshold value

1:8 ................................................ 1

1:4 ................................................ 1

1:2 ................................................ 2

1:1 ................................................ 3

2:1................................................ 5

4:1 ................................................ 9

8:1 ................................................ 17

* Multiple Programmable Full Threshold Constant configuration:

Aspect Ratio........Min assert threshold value........Min negate threshold value(prog_full_negate_min)

1:8 .................................................... 2 .........................................................1

1:4 .................................................... 2 .........................................................1

1:2 .................................................... 3 ........................................................ 2

1:1 .................................................... 4 ........................................................ 3

2:1 .................................................... 6 ........................................................ 5

4:1 ....................................................10 ....................................................... 9

8:1 ....................................................18 ...................................................... 17

Rule:

prog_full_negate_min <= prog_full_negate_value < prog_full_assert_val

The SPI-4.2 GUI will be fixed in FIFO Generator v4.1, expected in August/September 2007.

AR# 24937
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article