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AR# 2495

3.x FPGA Express - No MUX_OP is inferred for the case. (HDL-380)

Description

Keywords: FPGA Express, Synopsys, MUX_OP, case, HDL-380, VHDL, Verilog

Urgency: Standard

General Description:
Beginning with FPGA Express 3.0, users may see a new warning when synthesizing
case statements:

Warning: No MUX_OP inferred for the case in routine state_machine line XX in file
'<filename>.vhd' because it might lose the benefit of resource sharing. (HDL-380)

Solution

This warning is simply information about the synthesis of the design. FPGA Express
has seen that, for the specified case statement, inference of a mux would be less
optimal than the combinatorial logic that it infers; this is because a mux would prohibit
FPGA Express from investigating operator sharing for that case statement.

This warning can be safely ignored.

Furthermore, the environment variable listed in the extended Help does not apply to
the FPGA Express product, so do not attempt to set this variable.

For more information about MUX_OPs, please refer to (Xilinx Solution 11331).
AR# 2495
Date Created 06/27/1997
Last Updated 08/11/2003
Status Archive
Type General Article