UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24954

ML505 - ML505 reference design ZBT SRAM phase shift value has incorrect polarity in MHS file

Description

Intermittent failures with ZBT memory attributed to a non-optimal phase shift setting in the MHS file.

Solution

Update the phase shift value on the DCM used for the ZBT SRAM clock; change the phase shift from -64 to 64 (sign change).

Before

BEGIN dcm_module

PARAMETER INSTANCE = dcm_2

PARAMETER HW_VER = 1.00.a

PARAMETER C_CLKIN_PERIOD = 10.000000

PARAMETER C_EXT_RESET_HIGH = 0

PARAMETER C_CLK0_BUF = TRUE

PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED

PARAMETER C_PHASE_SHIFT = -64

PORT CLKIN = sys_clk_s

PORT CLK0 = sram_clk

PORT CLKFB = sram_clk_fb

PORT RST = dcm_1_lock

PORT LOCKED = dcm_locked

END

After

BEGIN dcm_module

PARAMETER INSTANCE = dcm_2

PARAMETER HW_VER = 1.00.a

PARAMETER C_CLKIN_PERIOD = 10.000000

PARAMETER C_EXT_RESET_HIGH = 0

PARAMETER C_CLK0_BUF = TRUE

PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED

PARAMETER C_PHASE_SHIFT = 64

PORT CLKIN = sys_clk_s

PORT CLK0 = sram_clk

PORT CLKFB = sram_clk_fb

PORT RST = dcm_1_lock

PORT LOCKED = dcm_locked

END

NOTE: For other ML505 board issues, perform an Answer Record search for ML505.

AR# 24954
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article